drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
authorManasi Navare <manasi.d.navare@intel.com>
Fri, 23 Mar 2018 17:24:15 +0000 (10:24 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 23 Mar 2018 21:56:27 +0000 (14:56 -0700)
commitc92f47b5ec977a31c72a3c3514ae460b3dd725ff
treeb701ba6e27b9b098d56d972dfaf729f6293b130f
parent19b904f8df5c6c1418769de35bf238ef72e49814
drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI

On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.

This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.

v4 (from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-4-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/i915_reg.h