drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Thu, 21 Nov 2024 11:27:26 +0000 (13:27 +0200)
committerVinod Govindapillai <vinod.govindapillai@intel.com>
Thu, 12 Dec 2024 07:28:47 +0000 (09:28 +0200)
commita831920c370c5b93901350154c6e4324b797b57b
tree4cc73dcb06214689b5daca105d77c6265e13fb14
parentaac49b862a855e170620f023fbca370fac763e33
drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip

Xe3 is capable of switching automatically to min ddb allocation
(not using any extra blocks) or interim SAGV-adjusted allocation
in case if async flip is used. Introduce the minimum and interim
ddb allocation configuration for that purpose. Also i915 is
replaced with intel_display within the patch's context

v2: update min/interim ddb declarations and handling (Ville)
    update to register definitions styling
    consolidation of minimal wm0 check with min DDB check

Bspec: 69880, 72053
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-4-vinod.govindapillai@intel.com
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/skl_universal_plane.c
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
drivers/gpu/drm/i915/display/skl_watermark.c