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(parent: d341db8) | patch
x86/msr: Add AMD CPPC MSR definitions
authorHuang Rui <ray.huang@amd.com>
Fri, 24 Dec 2021 01:04:56 +0000 (09:04 +0800)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 30 Dec 2021 17:51:17 +0000 (18:51 +0100)
commit89aa94b4a218339b08f052a28c55322d5a13fc9e
tree99eb9e4b1a3a6c5b7f7663f849d4d7e10f031842tree | snapshot
parentd341db8f48ea43314f489921962c7f8f4ec27239commit | diff
x86/msr: Add AMD CPPC MSR definitions

AMD CPPC (Collaborative Processor Performance Control) function uses MSR
registers to manage the performance hints. So add the MSR register macro
here.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
arch/x86/include/asm/msr-index.h diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)