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clk: rockchip: Add more PLL rates for rk3568
authorSascha Hauer <s.hauer@pengutronix.de>
Wed, 26 Jan 2022 14:55:33 +0000 (15:55 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 8 Feb 2022 11:56:33 +0000 (12:56 +0100)
commit842f4cb7263953020f4e2f2f0005fc3e6fc56144
tree796d4e6150d5e539bc4d3f997312bf9e7d0cfbfbtree
parente783362eb54cd99b2cac8b3a9aeac942e6f6ac07commit | diff
clk: rockchip: Add more PLL rates for rk3568

This adds a few more PLL settings needed for some standard resolutions:

297MHz    3840x2160-30.00
241.5MHz  2560x1440-59.95
135MHz    1280x1024-75.02
119MHz    1680x1050-59.88
108MHz    1280x1024-60.02
 78.75MHz 1024x768-75.03

Changes since v3:
- new patch

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)