1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
4 * Based on the bochs drm driver.
6 * Copyright (c) 2016 Huawei Limited.
9 * Rongrong Zou <zourongrong@huawei.com>
10 * Rongrong Zou <zourongrong@gmail.com>
11 * Jianhua Li <lijianhua@huawei.com>
14 #include <linux/module.h>
15 #include <linux/pci.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_gem_vram_helper.h>
20 #include <drm/drm_irq.h>
21 #include <drm/drm_managed.h>
22 #include <drm/drm_vblank.h>
24 #include "hibmc_drm_drv.h"
25 #include "hibmc_drm_regs.h"
27 DEFINE_DRM_GEM_FOPS(hibmc_fops);
29 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg)
31 struct drm_device *dev = (struct drm_device *)arg;
32 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
35 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
37 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
38 writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
39 priv->mmio + HIBMC_RAW_INTERRUPT);
40 drm_handle_vblank(dev, 0);
46 static const struct drm_driver hibmc_driver = {
47 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
51 .desc = "hibmc drm driver",
54 .debugfs_init = drm_vram_mm_debugfs_init,
55 .dumb_create = hibmc_dumb_create,
56 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset,
57 .gem_prime_mmap = drm_gem_prime_mmap,
58 .irq_handler = hibmc_drm_interrupt,
61 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
63 struct drm_device *drm_dev = dev_get_drvdata(dev);
65 return drm_mode_config_helper_suspend(drm_dev);
68 static int __maybe_unused hibmc_pm_resume(struct device *dev)
70 struct drm_device *drm_dev = dev_get_drvdata(dev);
72 return drm_mode_config_helper_resume(drm_dev);
75 static const struct dev_pm_ops hibmc_pm_ops = {
76 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
80 static int hibmc_kms_init(struct hibmc_drm_private *priv)
82 struct drm_device *dev = &priv->dev;
85 drm_mode_config_init(dev);
86 priv->mode_config_initialized = true;
88 dev->mode_config.min_width = 0;
89 dev->mode_config.min_height = 0;
90 dev->mode_config.max_width = 1920;
91 dev->mode_config.max_height = 1200;
93 dev->mode_config.fb_base = priv->fb_base;
94 dev->mode_config.preferred_depth = 32;
95 dev->mode_config.prefer_shadow = 1;
97 dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
99 ret = hibmc_de_init(priv);
101 drm_err(dev, "failed to init de: %d\n", ret);
105 ret = hibmc_vdac_init(priv);
107 drm_err(dev, "failed to init vdac: %d\n", ret);
114 static void hibmc_kms_fini(struct hibmc_drm_private *priv)
116 if (priv->mode_config_initialized) {
117 drm_mode_config_cleanup(&priv->dev);
118 priv->mode_config_initialized = false;
123 * It can operate in one of three modes: 0, 1 or Sleep.
125 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
127 u32 control_value = 0;
128 void __iomem *mmio = priv->mmio;
131 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
134 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
137 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
138 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
139 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
140 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
141 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
142 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
145 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
149 void __iomem *mmio = priv->mmio;
151 /* Get current power mode. */
152 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
153 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
156 case HIBMC_PW_MODE_CTL_MODE_MODE0:
157 gate_reg = HIBMC_MODE0_GATE;
160 case HIBMC_PW_MODE_CTL_MODE_MODE1:
161 gate_reg = HIBMC_MODE1_GATE;
165 gate_reg = HIBMC_MODE0_GATE;
168 writel(gate, mmio + gate_reg);
171 static void hibmc_hw_config(struct hibmc_drm_private *priv)
175 /* On hardware reset, power mode 0 is default. */
176 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
178 /* Enable display power gate & LOCALMEM power gate*/
179 reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
180 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
181 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
182 reg |= HIBMC_CURR_GATE_DISPLAY(1);
183 reg |= HIBMC_CURR_GATE_LOCALMEM(1);
185 hibmc_set_current_gate(priv, reg);
188 * Reset the memory controller. If the memory controller
189 * is not reset in chip,the system might hang when sw accesses
190 * the memory.The memory should be resetted after
191 * changing the MXCLK.
193 reg = readl(priv->mmio + HIBMC_MISC_CTRL);
194 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
195 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
196 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
198 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
199 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
201 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
204 static int hibmc_hw_map(struct hibmc_drm_private *priv)
206 struct drm_device *dev = &priv->dev;
207 struct pci_dev *pdev = dev->pdev;
208 resource_size_t addr, size, ioaddr, iosize;
210 ioaddr = pci_resource_start(pdev, 1);
211 iosize = pci_resource_len(pdev, 1);
212 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
214 drm_err(dev, "Cannot map mmio region\n");
218 addr = pci_resource_start(pdev, 0);
219 size = pci_resource_len(pdev, 0);
220 priv->fb_map = devm_ioremap(dev->dev, addr, size);
222 drm_err(dev, "Cannot map framebuffer\n");
225 priv->fb_base = addr;
226 priv->fb_size = size;
231 static int hibmc_hw_init(struct hibmc_drm_private *priv)
235 ret = hibmc_hw_map(priv);
239 hibmc_hw_config(priv);
244 static int hibmc_unload(struct drm_device *dev)
246 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
248 drm_atomic_helper_shutdown(dev);
250 pci_disable_msi(dev->pdev);
251 hibmc_kms_fini(priv);
253 dev->dev_private = NULL;
257 static int hibmc_load(struct drm_device *dev)
259 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
262 ret = hibmc_hw_init(priv);
266 ret = hibmc_mm_init(priv);
270 ret = hibmc_kms_init(priv);
274 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
276 drm_err(dev, "failed to initialize vblank: %d\n", ret);
280 ret = pci_enable_msi(dev->pdev);
282 drm_warn(dev, "enabling MSI failed: %d\n", ret);
284 ret = devm_drm_irq_install(dev, dev->pdev->irq);
286 drm_warn(dev, "install irq failed: %d\n", ret);
289 /* reset all the states of crtc/plane/encoder/connector */
290 drm_mode_config_reset(dev);
296 drm_err(dev, "failed to initialize drm driver: %d\n", ret);
300 static int hibmc_pci_probe(struct pci_dev *pdev,
301 const struct pci_device_id *ent)
303 struct hibmc_drm_private *priv;
304 struct drm_device *dev;
307 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev,
312 priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver,
313 struct hibmc_drm_private, dev);
315 DRM_ERROR("failed to allocate drm_device\n");
316 return PTR_ERR(priv);
321 pci_set_drvdata(pdev, dev);
323 ret = pci_enable_device(pdev);
325 drm_err(dev, "failed to enable pci device: %d\n", ret);
329 ret = hibmc_load(dev);
331 drm_err(dev, "failed to load hibmc: %d\n", ret);
335 ret = drm_dev_register(dev, 0);
337 drm_err(dev, "failed to register drv for userspace access: %d\n",
342 drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
349 pci_disable_device(pdev);
356 static void hibmc_pci_remove(struct pci_dev *pdev)
358 struct drm_device *dev = pci_get_drvdata(pdev);
360 drm_dev_unregister(dev);
365 static const struct pci_device_id hibmc_pci_table[] = {
366 { PCI_VDEVICE(HUAWEI, 0x1711) },
370 static struct pci_driver hibmc_pci_driver = {
372 .id_table = hibmc_pci_table,
373 .probe = hibmc_pci_probe,
374 .remove = hibmc_pci_remove,
375 .driver.pm = &hibmc_pm_ops,
378 module_pci_driver(hibmc_pci_driver);
380 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
381 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
382 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
383 MODULE_LICENSE("GPL v2");