riscv: Add support for non-coherent devices using zicbom extension
authorHeiko Stuebner <heiko@sntech.de>
Wed, 6 Jul 2022 23:15:35 +0000 (01:15 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 28 Jul 2022 22:30:51 +0000 (15:30 -0700)
commit1631ba1259d6d7f49b6028f2a1a0fa02be1c522a
tree224d5329d0ce1579c48f8f2b68b7a2c989dd9a96
parentd1afce6709595b39cd159bdc54fe2093808c02fc
riscv: Add support for non-coherent devices using zicbom extension

The Zicbom ISA-extension was ratified in november 2021
and introduces instructions for dcache invalidate, clean
and flush operations.

Implement cache management operations for non-coherent devices
based on them.

Of course not all cores will support this, so implement an
alternative-based mechanism that replaces empty instructions
with ones done around Zicbom instructions.

As discussed in previous versions, assume the platform
being coherent by default so that non-coherent devices need
to get marked accordingly by firmware.

Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig
arch/riscv/Makefile
arch/riscv/include/asm/cache.h
arch/riscv/include/asm/cacheflush.h
arch/riscv/include/asm/errata_list.h
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpu.c
arch/riscv/kernel/cpufeature.c
arch/riscv/kernel/setup.c
arch/riscv/mm/Makefile
arch/riscv/mm/dma-noncoherent.c [new file with mode: 0644]