Arnd Bergmann [Mon, 20 Dec 2021 14:19:43 +0000 (15:19 +0100)]
Merge branch 'arm/drivers' into for-next
* arm/drivers: (28 commits)
soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
media: staging: tegra-vde: Support generic power domain
spi: tegra20-slink: Add OPP support
mtd: rawnand: tegra: Add runtime PM and OPP support
mmc: sdhci-tegra: Add runtime PM and OPP support
pwm: tegra: Add runtime PM and OPP support
bus: tegra-gmi: Add runtime PM and OPP support
usb: chipidea: tegra: Add runtime PM and OPP support
soc/tegra: pmc: Rename core power domain
soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()
soc/tegra: pmc: Rename 3d power domains
soc/tegra: Enable runtime PM during OPP state-syncing
soc/tegra: regulators: Prepare for suspend
soc/tegra: fuse: Use resource-managed helpers
soc/tegra: fuse: Reset hardware
soc/tegra: pmc: Add reboot notifier
soc/tegra: Don't print error message when OPPs not available
...
Arnd Bergmann [Mon, 20 Dec 2021 14:19:28 +0000 (15:19 +0100)]
Merge branch 'arm/fixes' into for-next
* arm/fixes:
arm64: dts: lx2160a: fix scl-gpios property name
ARM: dts: imx6qdl-wandboard: Fix Ethernet support
Arnd Bergmann [Mon, 20 Dec 2021 14:19:24 +0000 (15:19 +0100)]
Merge branch 'arm/newsoc' into for-next
* arm/newsoc:
reset: starfive-jh7100: Fix 32bit compilation
Arnd Bergmann [Mon, 20 Dec 2021 14:07:57 +0000 (15:07 +0100)]
Merge tag 'imx-drivers-5.17' of git://git./linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.17:
- A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver
to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add
i.MX8MN display related domain support.
- Add optional continuous burst clock support for imx-weim bus driver.
- Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in
gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and
MIX domain.
* tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
bus: imx-weim: optionally enable continuous burst clock
soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active
soc: imx: gpcv2: Synchronously suspend MIX domains
Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 14:06:46 +0000 (15:06 +0100)]
Merge tag 'at91-soc-5.17' of git://git./linux/kernel/git/at91/linux into arm/drivers
AT91 SoC #1 for 5.17:
- one low priority fix about of_node_put() missing in PM code
* tag 'at91-soc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: pm: Add of_node_put() before goto
Link: https://lore.kernel.org/r/20211217164134.28566-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 13:38:17 +0000 (14:38 +0100)]
Merge tag 'tegra-for-5.17-soc' of git://git./linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.17-rc1
This set of changes contains some preparatory work that is shared by
several branches and trees to support DVFS via power domains.
There's also a bit of cleanup and improvements to reboot on chips that
use PSCI.
* tag 'tegra-for-5.17-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Rename core power domain
soc/tegra: pmc: Rename 3d power domains
soc/tegra: regulators: Prepare for suspend
soc/tegra: fuse: Use resource-managed helpers
soc/tegra: fuse: Reset hardware
soc/tegra: pmc: Add reboot notifier
soc/tegra: Don't print error message when OPPs not available
Link: https://lore.kernel.org/r/20211217162253.1801077-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Emil Renner Berthing [Mon, 20 Dec 2021 12:17:59 +0000 (13:17 +0100)]
reset: starfive-jh7100: Fix 32bit compilation
We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't
be defined when compiling on 32bit architectures:
On i386:
../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’:
../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration]
value = readq(reg_assert);
^~~~~
../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration]
writeq(value, reg_assert);
^~~~~~
On m68k:
drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1
make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2
make[1]: *** [Makefile:1969: drivers] Error 2
make: *** [Makefile:226: __sub-make] Error 2
Fixes:
0be3a1595bf8 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver")
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20211220121800.760846-1-kernel@esmil.dk'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 11:53:18 +0000 (12:53 +0100)]
Merge tag 'tegra-for-5.17-drivers' of git://git./linux/kernel/git/tegra/linux into arm/drivers
drivers: Changes for v5.17-rc1
This is an assortment of driver patches that rely on some of the changes
in the for-5.17/soc branch. These have all been acked by the respective
maintainers and go through the Tegra tree to more easily handle the
build dependency.
* tag 'tegra-for-5.17-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
media: staging: tegra-vde: Support generic power domain
spi: tegra20-slink: Add OPP support
mtd: rawnand: tegra: Add runtime PM and OPP support
mmc: sdhci-tegra: Add runtime PM and OPP support
pwm: tegra: Add runtime PM and OPP support
bus: tegra-gmi: Add runtime PM and OPP support
usb: chipidea: tegra: Add runtime PM and OPP support
soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()
soc/tegra: Enable runtime PM during OPP state-syncing
Link: https://lore.kernel.org/r/20211217162253.1801077-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 11:51:18 +0000 (12:51 +0100)]
Merge tag 'ti-driver-soc-fixes-for-v5.17' of git://git./linux/kernel/git/ti/linux into arm/drivers
SoC: Keystone driver update for v5.17
* k3-socinfo: Add entry for J721S2 SoC family
* Misc fixups for tisci, pruss, knav_dma
* tag 'ti-driver-soc-fixes-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_init
soc: ti: k3-socinfo: Add entry for J721S2 SoC family
firmware: ti_sci: rm: remove unneeded semicolon
soc: ti: pruss: fix referenced node in error message
Link: https://lore.kernel.org/r/20211217154921.cagzppcensxx6wm4@pension
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 11:37:20 +0000 (12:37 +0100)]
Merge tag 'imx-fixes-5.16-3' of git://git./linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.16, round 3:
- Fix imx6qdl-wandboard Ethernet support by adding 'qca,clk-out-frequency'
property.
- Fix scl-gpios property typo in LX2160A device tree.
* tag 'imx-fixes-5.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: lx2160a: fix scl-gpios property name
ARM: dts: imx6qdl-wandboard: Fix Ethernet support
soc: imx: Register SoC device only on i.MX boards
soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi reset
ARM: dts: imx6ull-pinfunc: Fix CSI_DATA07__ESAI_TX0 pad name
arm64: dts: imx8mq: remove interconnect property from lcdif
arm64: dts: ten64: remove redundant interrupt declaration for gpio-keys
arm64: dts: lx2160abluebox3: update RGMII delays for sja1105 switch
ARM: dts: ls1021a-tsn: update RGMII delays for sja1105 switch
ARM: dts: imx6qp-prtwd3: update RGMII delays for sja1105 switch
Link: https://lore.kernel.org/r/20211218052003.GA25102@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 15:11:23 +0000 (16:11 +0100)]
soc: document merges
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 15:09:59 +0000 (16:09 +0100)]
Merge branch 'arm/defconfig' into for-next
* arm/defconfig:
arm64: defconfig: Enable R-Car S4-8
Arnd Bergmann [Fri, 17 Dec 2021 15:09:43 +0000 (16:09 +0100)]
Merge branch 'arm/dt' into for-next
* arm/dt: (31 commits)
arm64: dts: renesas: Fix pin controller node names
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: allwinner: h6: Add Hantro G2 node
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
arm64: dts: renesas: r9a07g044: Add TSU node
arm64: dts: renesas: falcon-cpu: Add DSI display output
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: Add Renesas Spider boards support
arm64: dts: renesas: Add Renesas R8A779F0 SoC support
dt-bindings: arm: renesas: Document Renesas Spider boards
arm64: dts: renesas: Fix thermal bindings
arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
arm64: dts: allwinner: h6: tanix: Add MMC1 node
arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
dt-bindings: arm: sunxi: Add Tanix TX6 mini
arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
ARM: dts: sun8i: Adjust power key nodes
arm64: dts: allwinner: a64: Update MBUS node
ARM: dts: sunxi: h3/h5: Update MBUS node
...
Arnd Bergmann [Fri, 17 Dec 2021 15:09:36 +0000 (16:09 +0100)]
Merge branch 'arm/drivers' into for-next
* arm/drivers:
soc: renesas: rcar-rst: Add support for R-Car S4-8
soc: renesas: Identify R-Car S4-8
soc: renesas: r8a779f0-sysc: Add r8a779f0 support
soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
Arnd Bergmann [Fri, 17 Dec 2021 15:09:27 +0000 (16:09 +0100)]
Merge branch 'arm/fixes' into for-next
* arm/fixes:
optee: Suppress false positive kmemleak report in optee_handle_rpc()
tee: optee: Fix incorrect page free bug
tee: handle lookup of shm with reference count 0
bus: sunxi-rsb: Fix shutdown
arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode
Arnd Bergmann [Fri, 17 Dec 2021 15:07:02 +0000 (16:07 +0100)]
Merge tag 'renesas-arm-defconfig-for-v5.17-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/defconfig
Renesas ARM defconfig updates for v5.17
- Enable support for the new R-Car S4-8 SoC in the arm64 defconfig.
* tag 'renesas-arm-defconfig-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable R-Car S4-8
Link: https://lore.kernel.org/r/cover.1639736717.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 15:04:54 +0000 (16:04 +0100)]
Merge tag 'sunxi-drivers-for-5.17-1' of git://git./linux/kernel/git/sunxi/linux into arm/fixes
Some new drivers changes for the Allwinner SoCs, fixing the shutdown
path of the RSB driver
* tag 'sunxi-drivers-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
bus: sunxi-rsb: Fix shutdown
Link: https://lore.kernel.org/r/6f2f75ad-de62-49a4-82a4-8655a567a09e.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:58:16 +0000 (15:58 +0100)]
Merge tag 'renesas-drivers-for-v5.17-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.17 (take two)
- Core support for the R-Car S4-8 (R8A779F0) SoC, including System
Controller (SYSC) and Reset (RST) support.
* tag 'renesas-drivers-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: rcar-rst: Add support for R-Car S4-8
soc: renesas: Identify R-Car S4-8
soc: renesas: r8a779f0-sysc: Add r8a779f0 support
soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
Link: https://lore.kernel.org/r/cover.1639736722.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:54:22 +0000 (15:54 +0100)]
Merge tag 'renesas-dt-bindings-for-v5.17-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.17 (take two)
- Document support for the R-Car S4-8 Spider CPU and BreakOut boards.
* tag 'renesas-dt-bindings-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document Renesas Spider boards
Link: https://lore.kernel.org/r/cover.1639736725.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:53:29 +0000 (15:53 +0100)]
Merge tag 'renesas-arm-dt-for-v5.17-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.17 (take two)
- Initial support for the R-Car S4-8 SoC on the Spider CPU and
BreakOut boards,
- MIPI DSI display support for the R-Car V3u SoC and the Falcon board
stack,
- Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Fix pin controller node names
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
arm64: dts: renesas: r9a07g044: Add TSU node
arm64: dts: renesas: falcon-cpu: Add DSI display output
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: Add Renesas Spider boards support
arm64: dts: renesas: Add Renesas R8A779F0 SoC support
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
arm64: dts: renesas: Fix thermal bindings
Link: https://lore.kernel.org/r/cover.1639736718.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:52:07 +0000 (15:52 +0100)]
Merge tag 'sunxi-dt-for-5.17-1' of git://git./linux/kernel/git/sunxi/linux into arm/dt
Our usual round of DT patches for the 5.17 merge window, with:
- Introduction of the chassis-type property
- I2C, SPDIF support for the Tanix TX6
- Memory frequency scaling for the A64 and H5
- Hantro G2 support for the H6
- New Board: Tanix TX6 Mini
* tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: Add Hantro G2 node
arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
arm64: dts: allwinner: h6: tanix: Add MMC1 node
arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
dt-bindings: arm: sunxi: Add Tanix TX6 mini
arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
ARM: dts: sun8i: Adjust power key nodes
arm64: dts: allwinner: a64: Update MBUS node
ARM: dts: sunxi: h3/h5: Update MBUS node
dt-bindings: arm: sunxi: Add H5 MBUS compatible
dt-bindings: arm: sunxi: Expand MBUS binding
dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq
dt-bindings: crypto: Add optional dma properties
ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
ARM: dts: sunxi: Add CEC clock to DW-HDMI
arm64: dts: allwinner: a64: Add CEC clock to HDMI
ARM: dts: sun8i: h3: beelink-x2: Sort nodes
arm64: dts: allwinner: h6: tanix-tx6: Add I2C node
arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF
arm64: dts: allwinner: add 'chassis-type' property
Link: https://lore.kernel.org/r/ef385139-6fd4-42d2-9bfe-a4dda7ac76c9.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:51:29 +0000 (15:51 +0100)]
Merge tag 'sunxi-fixes-for-5.16-1' of git://git./linux/kernel/git/sunxi/linux into arm/fixes
One patch to fix the GMAC PHY mode on the OrangePi Zero Plus
* tag 'sunxi-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode
Link: https://lore.kernel.org/r/e295f1f7-cd24-4a7a-ae83-aafb2a3263b6.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:51:15 +0000 (15:51 +0100)]
Merge tag 'fixes-for-v5.16' of https://git.linaro.org/people/jens.wiklander/linux-tee into arm/fixes
TEE and OP-TEE fixes for v5.16
- Fixes a race when a tee_shm reaches reference count 0 and is about to
be teared down
- Fixes an incorrect page free bug in an error path of the OP-TEE shared
memory pool handling
- Suppresses a false positive kmemleak report when allocating driver
private shared memory buffers for OP-TEE
* tag 'fixes-for-v5.16' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: Suppress false positive kmemleak report in optee_handle_rpc()
tee: optee: Fix incorrect page free bug
tee: handle lookup of shm with reference count 0
Link: https://lore.kernel.org/r/20211216150745.GA3347954@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Geert Uytterhoeven [Thu, 16 Dec 2021 15:04:49 +0000 (16:04 +0100)]
arm64: dts: renesas: Fix pin controller node names
Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
Adam Ford [Wed, 15 Dec 2021 00:46:22 +0000 (18:46 -0600)]
soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
This adds the description for the i.MX8MN disp blk-ctrl.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:20 +0000 (18:46 -0600)]
dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
This adds the defines for the power domains provided by the DISP
blk-ctrl.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:19 +0000 (18:46 -0600)]
soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
The dispmix will be needed for the blkctl driver, so add it
to the gpcv2.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:18 +0000 (18:46 -0600)]
soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
Like the i.MX8MM, keep the gpumix clocks running when the
domain is active.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Arnd Bergmann [Thu, 16 Dec 2021 16:55:25 +0000 (17:55 +0100)]
soc: document merges
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 16 Dec 2021 16:53:55 +0000 (17:53 +0100)]
Merge branch 'arm/newsoc' into for-next
* arm/newsoc:
RISC-V: Add BeagleV Starlight Beta device tree
RISC-V: Add initial StarFive JH7100 device tree
serial: 8250_dw: Add StarFive JH7100 quirk
dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
pinctrl: starfive: Add pinctrl driver for StarFive SoCs
dt-bindings: pinctrl: Add StarFive JH7100 bindings
dt-bindings: pinctrl: Add StarFive pinctrl definitions
reset: starfive-jh7100: Add StarFive JH7100 reset driver
dt-bindings: reset: Add Starfive JH7100 reset bindings
dt-bindings: reset: Add StarFive JH7100 reset definitions
clk: starfive: Add JH7100 clock generator driver
dt-bindings: clock: starfive: Add JH7100 bindings
dt-bindings: clock: starfive: Add JH7100 clock definitions
dt-bindings: interrupt-controller: Add StarFive JH7100 plic
dt-bindings: timer: Add StarFive JH7100 clint
RISC-V: Add StarFive SoC Kconfig option
Arnd Bergmann [Thu, 16 Dec 2021 16:51:38 +0000 (17:51 +0100)]
Merge tag 'jh7100-for-5.17' of https://github.com/esmil/linux into arm/newsoc
Basic StarFive JH7100 RISC-V SoC support
This adds support for the StarFive JH7100 RISC-V SoC. The SoC has many
devices that need non-coherent DMA operations to work which isn't
upstream yet[1], so this just adds basic support to boot up, get a
serial console, blink an LED and reboot itself. Unlike the Allwinner D1
this chip doesn't use any extra pagetable bits, but instead the DDR RAM
appears twice in the memory map, with and without the cache.
The JH7100 is a test chip for the upcoming JH7110 and about 300 BeagleV
Starlight Beta boards were sent out with them as part of a now cancelled
BeagleBoard.org project. However StarFive has produced more of the
JH7100s and will be selling VisionFive boards with them soon[2].
[1]: https://lore.kernel.org/linux-riscv/
20210723214031.
3251801-2-atish.patra@wdc.com/
[2]: https://www.cnx-software.com/2021/12/09/starfive-visionfive-single-board-computer-for-sale-accelerating-risc-v-ecosystem-development/
* tag 'jh7100-for-5.17' of https://github.com/esmil/linux:
RISC-V: Add BeagleV Starlight Beta device tree
RISC-V: Add initial StarFive JH7100 device tree
serial: 8250_dw: Add StarFive JH7100 quirk
dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
pinctrl: starfive: Add pinctrl driver for StarFive SoCs
dt-bindings: pinctrl: Add StarFive JH7100 bindings
dt-bindings: pinctrl: Add StarFive pinctrl definitions
reset: starfive-jh7100: Add StarFive JH7100 reset driver
dt-bindings: reset: Add Starfive JH7100 reset bindings
dt-bindings: reset: Add StarFive JH7100 reset definitions
clk: starfive: Add JH7100 clock generator driver
dt-bindings: clock: starfive: Add JH7100 bindings
dt-bindings: clock: starfive: Add JH7100 clock definitions
dt-bindings: interrupt-controller: Add StarFive JH7100 plic
dt-bindings: timer: Add StarFive JH7100 clint
RISC-V: Add StarFive SoC Kconfig option
Link: https://lore.kernel.org/r/20211216164205.286138-1-kernel@esmil.dk
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Emil Renner Berthing [Sun, 10 Oct 2021 17:48:36 +0000 (19:48 +0200)]
RISC-V: Add BeagleV Starlight Beta device tree
Add initial device tree for the BeagleV Starlight Beta board. About 300
of these boards were sent out as part of a now cancelled BeagleBoard.org
project.
I2C timing data is based on the device tree in the vendor u-boot port.
Heartbeat LED added by Geert.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Sun, 10 Oct 2021 14:48:27 +0000 (16:48 +0200)]
RISC-V: Add initial StarFive JH7100 device tree
Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.
The CPU and cache data is based on the device tree in the vendor u-boot
port.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Mon, 4 Oct 2021 17:40:29 +0000 (19:40 +0200)]
serial: 8250_dw: Add StarFive JH7100 quirk
On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
exactly 16 * 115200Hz and many other common bitrates. Trying this will
only result in a higher input clock, but low enough that the UART's
internal divisor can't come close enough to the baud rate target.
So rather than try to set the input clock it's better to skip the
clk_set_rate call and rely solely on the UART's internal divisor.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Thu, 7 Oct 2021 12:24:29 +0000 (14:24 +0200)]
dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
Add compatibles for the StarFive JH7100 uarts.
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Tue, 6 Jul 2021 18:19:06 +0000 (20:19 +0200)]
pinctrl: starfive: Add pinctrl driver for StarFive SoCs
Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.
For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.
I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.
Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Co-developed-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Tue, 27 Jul 2021 12:34:33 +0000 (14:34 +0200)]
dt-bindings: pinctrl: Add StarFive JH7100 bindings
Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Tue, 6 Jul 2021 18:19:06 +0000 (20:19 +0200)]
dt-bindings: pinctrl: Add StarFive pinctrl definitions
Add definitons for pins and GPIO input, output and output enable
signals on the StarFive JH7100 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Sun, 19 Sep 2021 12:21:05 +0000 (14:21 +0200)]
reset: starfive-jh7100: Add StarFive JH7100 reset driver
Add a driver for the StarFive JH7100 reset controller.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Emil Renner Berthing [Sun, 19 Sep 2021 12:34:34 +0000 (14:34 +0200)]
dt-bindings: reset: Add Starfive JH7100 reset bindings
Add bindings for the reset controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Geert Uytterhoeven [Fri, 25 Jun 2021 09:30:00 +0000 (11:30 +0200)]
dt-bindings: reset: Add StarFive JH7100 reset definitions
Add all resets for the StarFive JH7100 reset controller.
Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
to all definitions.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Geert Uytterhoeven [Tue, 1 Jun 2021 13:57:52 +0000 (15:57 +0200)]
clk: starfive: Add JH7100 clock generator driver
Add a driver for the StarFive JH7100 clock generator.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Geert Uytterhoeven [Tue, 1 Jun 2021 14:02:23 +0000 (16:02 +0200)]
dt-bindings: clock: starfive: Add JH7100 bindings
Add bindings for the clock generator on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Geert Uytterhoeven [Fri, 25 Jun 2021 09:29:51 +0000 (11:29 +0200)]
dt-bindings: clock: starfive: Add JH7100 clock definitions
Add all clock outputs for the StarFive JH7100 clock generator.
Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
to all definitions.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Biju Das [Wed, 8 Dec 2021 10:40:26 +0000 (10:40 +0000)]
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
Add vdd core regulator (1.1 V).
This patch add regulator support for gpu.
The H/W manual mentions nothing about a gpu regulator. So using vdd
core regulator for gpu.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 8 Dec 2021 10:40:25 +0000 (10:40 +0000)]
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Xiaolei Wang [Mon, 6 Dec 2021 12:05:33 +0000 (20:05 +0800)]
optee: Suppress false positive kmemleak report in optee_handle_rpc()
We observed the following kmemleak report:
unreferenced object 0xffff000007904500 (size 128):
comm "swapper/0", pid 1, jiffies
4294892671 (age 44.036s)
hex dump (first 32 bytes):
00 47 90 07 00 00 ff ff 60 00 c0 ff 00 00 00 00 .G......`.......
60 00 80 13 00 80 ff ff a0 00 00 00 00 00 00 00 `...............
backtrace:
[<
000000004c12b1c7>] kmem_cache_alloc+0x1ac/0x2f4
[<
000000005d23eb4f>] tee_shm_alloc+0x78/0x230
[<
00000000794dd22c>] optee_handle_rpc+0x60/0x6f0
[<
00000000d9f7c52d>] optee_do_call_with_arg+0x17c/0x1dc
[<
00000000c35884da>] optee_open_session+0x128/0x1ec
[<
000000001748f2ff>] tee_client_open_session+0x28/0x40
[<
00000000aecb5389>] optee_enumerate_devices+0x84/0x2a0
[<
000000003df18bf1>] optee_probe+0x674/0x6cc
[<
000000003a4a534a>] platform_drv_probe+0x54/0xb0
[<
000000000c51ce7d>] really_probe+0xe4/0x4d0
[<
000000002f04c865>] driver_probe_device+0x58/0xc0
[<
00000000b485397d>] device_driver_attach+0xc0/0xd0
[<
00000000c835f0df>] __driver_attach+0x84/0x124
[<
000000008e5a429c>] bus_for_each_dev+0x70/0xc0
[<
000000001735e8a8>] driver_attach+0x24/0x30
[<
000000006d94b04f>] bus_add_driver+0x104/0x1ec
This is not a memory leak because we pass the share memory pointer
to secure world and would get it from secure world before releasing it.
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Sumit Garg [Thu, 16 Dec 2021 05:47:25 +0000 (11:17 +0530)]
tee: optee: Fix incorrect page free bug
Pointer to the allocated pages (struct page *page) has already
progressed towards the end of allocation. It is incorrect to perform
__free_pages(page, order) using this pointer as we would free any
arbitrary pages. Fix this by stop modifying the page pointer.
Fixes:
ec185dd3ab25 ("optee: Fix memory leak when failing to register shm pages")
Cc: stable@vger.kernel.org
Reported-by: Patrik Lantz <patrik.lantz@axis.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Tyler Hicks <tyhicks@linux.microsoft.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Arnd Bergmann [Thu, 16 Dec 2021 14:15:46 +0000 (15:15 +0100)]
soc: document merges
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 16 Dec 2021 14:03:03 +0000 (15:03 +0100)]
Merge branch 'arm/fixes' into for-next
* arm/fixes:
soc/tegra: fuse: Fix bitwise vs. logical OR warning
Arnd Bergmann [Thu, 16 Dec 2021 14:03:00 +0000 (15:03 +0100)]
Merge branch 'arm/dt' into for-next
* arm/dt:
ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp.
ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value
ARM: dts: am437x-gp-evm: enable ADC1
ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module
ARM: dts: am437x-cm-t43: Use a correctly spelled DT property
ARM: dts: am335x-icev2: Add system-power-controller to RTC node
ARM: dts: am335x-boneblack-common: move system-power-controller
ARM: dts: elpida_ecb240abacn: Change Elpida compatible
arm64: dts: Update NAND MTD partition for Agilex and Stratix 10
arm64: dts: n5x: add qspi, usb, and ethernet support
Arnd Bergmann [Thu, 16 Dec 2021 14:02:25 +0000 (15:02 +0100)]
Merge tag 'tegra-for-5.16-soc-fixes' of git://git./linux/kernel/git/tegra/linux into arm/fixes
soc/tegra: Fixes for v5.16-rc6
This contains a single build fix without which ARM allmodconfig builds
are broken if -Werror is enabled.
* tag 'tegra-for-5.16-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Fix bitwise vs. logical OR warning
Link: https://lore.kernel.org/r/20211215162618.3568474-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 16 Dec 2021 14:00:32 +0000 (15:00 +0100)]
Merge tag 'omap-for-v5.17/dt-signed' of git://git./linux/kernel/git/tmlind/linux-omap into arm/dt
Devicetree changes for omaps for v5.17 merge window
These changes are mostly minor non-urgent fixes for typos and binding checks.
The system-power-controller gets configured for more am3 devices as it's not
am335x-boneblack speicif. For for am437x we add magnetic card reader support.
Note that the asahi-kasei,ak8975 binding changes may produce a new binding
check warning as the binding related change is merged separately.
* tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp.
ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value
ARM: dts: am437x-gp-evm: enable ADC1
ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module
ARM: dts: am437x-cm-t43: Use a correctly spelled DT property
ARM: dts: am335x-icev2: Add system-power-controller to RTC node
ARM: dts: am335x-boneblack-common: move system-power-controller
ARM: dts: elpida_ecb240abacn: Change Elpida compatible
Link: https://lore.kernel.org/r/pull-1639659798-679261@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 16 Dec 2021 13:51:42 +0000 (14:51 +0100)]
Merge tag 'socfpga_dts_update_for_v5.17' of git://git./linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v5.17
- Update N5X to include qspi, usb and ethernet
- Adjust NAND partition size for Agilex and Stratix10
* tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: Update NAND MTD partition for Agilex and Stratix 10
arm64: dts: n5x: add qspi, usb, and ethernet support
Link: https://lore.kernel.org/r/20211215164545.300273-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:34 +0000 (02:23 +0300)]
media: staging: tegra-vde: Support generic power domain
Currently driver supports legacy power domain API, this patch adds generic
power domain support. This allows us to utilize a modern GENPD API for
newer device-trees.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:31 +0000 (02:23 +0300)]
spi: tegra20-slink: Add OPP support
The SPI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SPI driver must use OPP
API for driving the controller's clock rate because OPP API takes care
of reconfiguring the domain's performance state in accordance to the
rate. Add OPP support to the driver.
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:30 +0000 (02:23 +0300)]
mtd: rawnand: tegra: Add runtime PM and OPP support
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now NAND must be resumed using
runtime PM API in order to initialize the NAND power state. Add runtime PM
and OPP support to the NAND driver.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:29 +0000 (02:23 +0300)]
mmc: sdhci-tegra: Add runtime PM and OPP support
The SDHCI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SDHCI must be resumed using
runtime PM API in order to initialize the SDHCI power state. The SDHCI
clock rate must be changed using OPP API that will reconfigure the power
domain performance state in accordance to the rate. Add runtime PM and OPP
support to the SDHCI driver.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:28 +0000 (02:23 +0300)]
pwm: tegra: Add runtime PM and OPP support
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance state in accordance to the rate. Add runtime PM and OPP
support to the PWM driver.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:27 +0000 (02:23 +0300)]
bus: tegra-gmi: Add runtime PM and OPP support
The GMI bus on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now GMI must be resumed using
runtime PM API in order to initialize the GMI power state. Add runtime PM
and OPP support to the GMI driver.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:26 +0000 (02:23 +0300)]
usb: chipidea: tegra: Add runtime PM and OPP support
The Tegra USB controller belongs to the core power domain and we're going
to enable GENPD support for the core domain. Now USB controller must be
resumed using runtime PM API in order to initialize the USB power state.
We already support runtime PM for the CI device, but CI's PM is separated
from the RPM managed by tegra-usb driver. Add runtime PM and OPP support
to the driver.
Acked-by: Peter Chen <peter.chen@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 16 Dec 2021 13:05:06 +0000 (14:05 +0100)]
Merge branch 'tegra-for-5.17-soc-opp' of git://git./linux/kernel/git/tegra/linux into for-5.17/drivers
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:39 +0000 (02:23 +0300)]
soc/tegra: pmc: Rename core power domain
CORE power domain uses name of device-tree node, which is inconsistent with
the names of PMC domains. Set the name to "core" to make it consistent.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:09 +0000 (02:23 +0300)]
soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()
Only couple drivers need to get the -ENODEV error code and majority of
drivers need to explicitly initialize the performance state. Add new
common helper which sets up OPP table for these drivers.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:38 +0000 (02:23 +0300)]
soc/tegra: pmc: Rename 3d power domains
Device-tree schema doesn't allow domain name to start with a number.
We don't use 3d domain yet in device-trees, so rename it to the name
used by Tegra TRMs: TD, TD2.
Reported-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:08 +0000 (02:23 +0300)]
soc/tegra: Enable runtime PM during OPP state-syncing
GENPD core now can set up domain's performance state properly while device
is RPM-suspended. Runtime PM of a device must be enabled during setup
because GENPD checks whether device is suspended and check doesn't work
while RPM is disabled. Instead of replicating the boilerplate RPM-enable
code around OPP helper for each driver, let's make OPP helper to take care
of enabling it.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:37 +0000 (02:23 +0300)]
soc/tegra: regulators: Prepare for suspend
Depending on hardware version, Tegra SoC may require a higher voltages
during resume from system suspend, otherwise hardware will crash. Set
SoC voltages to a nominal levels during suspend.
Link: https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf057@gmail.com/
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:36 +0000 (02:23 +0300)]
soc/tegra: fuse: Use resource-managed helpers
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:35 +0000 (02:23 +0300)]
soc/tegra: fuse: Reset hardware
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Tue, 30 Nov 2021 11:44:06 +0000 (11:44 +0000)]
soc/tegra: pmc: Add reboot notifier
The Tegra PMC driver implements a restart handler that supports Tegra
specific reboot commands such as placing the device into 'recovery' mode
in order to reprogram the platform. This is accomplished by setting the
appropriate bit in the PMC scratch0 register prior to rebooting the
platform.
For Tegra platforms that support PSCI or EFI, the default Tegra restart
handler is not called and the PSCI or EFI restart handler is called
instead. Hence, for Tegra platforms that support PSCI or EFI, the Tegra
specific reboot commands do not currently work. Fix this by moving the
code that programs the PMC scratch0 register into a separate reboot
notifier that will always be called on reboot.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:10 +0000 (02:23 +0300)]
soc/tegra: Don't print error message when OPPs not available
Previously we assumed that devm_tegra_core_dev_init_opp_table() will
be used only by drivers that will always have device with OPP table,
but this is not true anymore. For example now Tegra30 will have OPP table
for PWM, but Tegra20 not and both use the same driver. Hence let's not
print the error message about missing OPP table in the common helper,
we can print it elsewhere.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Miaoqian Lin [Tue, 14 Dec 2021 01:55:44 +0000 (01:55 +0000)]
soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_init
Since devm_ioremap_resource() function return error pointers.
The pktdma_get_regs() function does not return NULL, It return error
pointers too. Using IS_ERR() to check the return value to fix this.
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20211214015544.7270-1-linmq006@gmail.com
Zhang Ying-22455 [Tue, 14 Dec 2021 07:23:33 +0000 (01:23 -0600)]
arm64: dts: lx2160a: fix scl-gpios property name
Fix the typo in the property name.
Fixes:
d548c217c6a3c ("arm64: dts: add QorIQ LX2160A SoC support")
Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Jens Wiklander [Thu, 9 Dec 2021 14:59:37 +0000 (15:59 +0100)]
tee: handle lookup of shm with reference count 0
Since the tee subsystem does not keep a strong reference to its idle
shared memory buffers, it races with other threads that try to destroy a
shared memory through a close of its dma-buf fd or by unmapping the
memory.
In tee_shm_get_from_id() when a lookup in teedev->idr has been
successful, it is possible that the tee_shm is in the dma-buf teardown
path, but that path is blocked by the teedev mutex. Since we don't have
an API to tell if the tee_shm is in the dma-buf teardown path or not we
must find another way of detecting this condition.
Fix this by doing the reference counting directly on the tee_shm using a
new refcount_t refcount field. dma-buf is replaced by using
anon_inode_getfd() instead, this separates the life-cycle of the
underlying file from the tee_shm. tee_shm_put() is updated to hold the
mutex when decreasing the refcount to 0 and then remove the tee_shm from
teedev->idr before releasing the mutex. This means that the tee_shm can
never be found unless it has a refcount larger than 0.
Fixes:
967c9cca2cc5 ("tee: generic TEE subsystem")
Cc: stable@vger.kernel.org
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Lars Persson <larper@axis.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reported-by: Patrik Lantz <patrik.lantz@axis.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jernej Skrabec [Mon, 29 Nov 2021 18:26:33 +0000 (19:26 +0100)]
arm64: dts: allwinner: h6: Add Hantro G2 node
H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly
older design, though.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com
Martin Haaß [Sun, 12 Dec 2021 12:30:30 +0000 (09:30 -0300)]
ARM: dts: imx6qdl-wandboard: Fix Ethernet support
Currently, the imx6q-wandboard Ethernet does not transmit any
data.
This issue has been exposed by commit
f5d9aa79dfdf ("ARM: imx6q:
remove clk-out fixup for the Atheros AR8031 and AR8035 PHYs").
Fix it by describing the qca,clk-out-frequency property as suggested
by the commit above.
Fixes:
77591e42458d ("ARM: dts: imx6qdl-wandboard: add ethernet PHY description")
Signed-off-by: Martin Haaß <vvvrrooomm@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Nathan Chancellor [Fri, 10 Dec 2021 16:55:29 +0000 (09:55 -0700)]
soc/tegra: fuse: Fix bitwise vs. logical OR warning
A new warning in clang points out two instances where boolean
expressions are being used with a bitwise OR instead of logical OR:
drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical]
reg = tegra_fuse_read_spare(i) |
^~~~~~~~~~~~~~~~~~~~~~~~~~
||
drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: note: cast one or both operands to int to silence this warning
drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical]
reg = tegra_fuse_read_spare(i) |
^~~~~~~~~~~~~~~~~~~~~~~~~~
||
drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: note: cast one or both operands to int to silence this warning
2 warnings generated.
The motivation for the warning is that logical operations short circuit
while bitwise operations do not.
In this instance, tegra_fuse_read_spare() is not semantically returning
a boolean, it is returning a bit value. Use u32 for its return type so
that it can be used with either bitwise or boolean operators without any
warnings.
Fixes:
25cd5a391478 ("ARM: tegra: Add speedo-based process identification")
Link: https://github.com/ClangBuiltLinux/linux/issues/1488
Suggested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Arnd Bergmann [Wed, 15 Dec 2021 15:01:21 +0000 (16:01 +0100)]
soc: document merges
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 15 Dec 2021 14:59:52 +0000 (15:59 +0100)]
Merge branch 'arm/drivers' into for-next
* arm/drivers:
soc: apple: apple-pmgr-pwrstate: Do not build as a module
soc: apple: apple-pmgr-pwrstate: Add auto-PM min level support
Arnd Bergmann [Wed, 15 Dec 2021 14:59:43 +0000 (15:59 +0100)]
Merge branch 'arm/dt' into for-next
* arm/dt:
dt-bindings: mailbox: apple,mailbox: Add power-domains property
arm64: dts: apple: t8103: Sort nodes by address
arm64: dts: apple: t8103: Rename clk24 to clkref
arm64: dts: apple: t8103: Add watchdog node
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible
dt-bindings: pci: apple,pcie: Add t6000 support
dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible
dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles
arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes
dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop
arm64: dts: apple: t8103: Remove PCIe max-link-speed properties
ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2
ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk
ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards
ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 15 Dec 2021 14:58:53 +0000 (15:58 +0100)]
Merge branch 'arm/soc' into for-next
* arm/soc:
ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h
ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X
Arnd Bergmann [Wed, 15 Dec 2021 14:58:00 +0000 (15:58 +0100)]
Merge tag 'asahi-soc-pmgr-5.17-v2' of https://github.com/AsahiLinux/linux into arm/drivers
Apple SoC PMGR driver updates for 5.17
* Adds an auto-PM feature that is necessary for a single device
* Disables module builds, which were broken anyway
* tag 'asahi-soc-pmgr-5.17-v2' of https://github.com/AsahiLinux/linux:
soc: apple: apple-pmgr-pwrstate: Do not build as a module
soc: apple: apple-pmgr-pwrstate: Add auto-PM min level support
Link: https://lore.kernel.org/r/660f6f7f-0857-b54c-c415-79bcb93f0e02@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 15 Dec 2021 14:56:39 +0000 (15:56 +0100)]
Merge tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 5.17, round 2:
- Various cleanups (removing useless props, sorting nodes, renaming
things)
- Add PMGR min-state binding & props (see PMGR pull for driver change)
- Initial compatibles for t600x machines (M1 Pro/Max). This covers the
bindings that just need compatible bumps & minor tweaks, no driver
changes.
- Add watchdog node (driver not merged yet, hopefully will be; binding
went in the previous pull)
- Add missing power-domains property to the mailbox binding
* tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux:
dt-bindings: mailbox: apple,mailbox: Add power-domains property
arm64: dts: apple: t8103: Sort nodes by address
arm64: dts: apple: t8103: Rename clk24 to clkref
arm64: dts: apple: t8103: Add watchdog node
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible
dt-bindings: pci: apple,pcie: Add t6000 support
dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible
dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles
arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes
dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop
arm64: dts: apple: t8103: Remove PCIe max-link-speed properties
Link: https://lore.kernel.org/r/a24faafd-f2ae-c3a7-5327-b27da7d9e34b@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 15 Dec 2021 14:55:30 +0000 (15:55 +0100)]
Merge tag 'stm32-dt-for-v5.17-1' of git://git./linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.17, round 1
Highlights:
----------
-MCU:
- fix ili9341 for dtbs_check warnings on stm32f429 disco.
- MPU:
- ST boards:
- tune HS USB phys on stm32mp15 EV1 and DKx boards.
- add pull-up on USART3/UART7 RX pins on STM32MP15 DKx boards.
- use correct pinctrl setting for STUSB1600 on STM32MP15 DK boards.
- ENGICAM:
- enable LVDS pannel on i.Core STM32MP1 EDIMM2.2.
- add "i.Core STM32MP1 C.TOUCH 2.0 10.1" OF" support:
EDIMM compliant general purpose carrier board with ETH 10/100,
WIFI/BT, CAN, ...
* tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2
ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk
ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards
ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco
Link: https://lore.kernel.org/r/dfe942db-5af7-bb82-22b6-3bd866c9017d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Hector Martin [Wed, 15 Dec 2021 11:27:54 +0000 (20:27 +0900)]
soc: apple: apple-pmgr-pwrstate: Do not build as a module
This doesn't make any sense as a module since it is a critical device,
and it turns out of_phandle_iterator_args was not exported so the module
version doesn't build anyway.
Fixes:
6df9d38f9146 ("soc: apple: Add driver for Apple PMGR power state controls")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Thu, 9 Dec 2021 04:50:42 +0000 (13:50 +0900)]
dt-bindings: mailbox: apple,mailbox: Add power-domains property
This will bind to the PMGR pwrstate nodes that control power/clock
gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so
initially this will just keep the domain on permanently.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Sun, 12 Dec 2021 01:40:16 +0000 (10:40 +0900)]
arm64: dts: apple: t8103: Sort nodes by address
We decided to keep SoC nodes sorted by address for sanity; fix a couple
that slipped into the wrong place.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Tue, 5 Oct 2021 14:24:21 +0000 (23:24 +0900)]
arm64: dts: apple: t8103: Rename clk24 to clkref
We now know that this frequency comes from the external reference
oscillator and is used for various SoC blocks, and isn't just a random
24MHz clock, so let's call it something more appropriate.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Arnd Bergmann [Tue, 14 Dec 2021 21:41:32 +0000 (22:41 +0100)]
Merge tag 'ixp4xx-arm-soc-v5.17' of git://git./linux/kernel/git/linusw/linux-nomadik into arm/soc
Some IXP4xx SoC and driver related changes for v5.17:
- Drop unused Kconfig options
- Drop unused platform data header file
* tag 'ixp4xx-arm-soc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h
ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X
Link: https://lore.kernel.org/r/CACRpkdZXZBpexMUuwTV-RB7_QAjBQkSbRsaBtgFShcqxuNTUgw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 14 Dec 2021 21:35:44 +0000 (22:35 +0100)]
soc: document merges
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 14 Dec 2021 21:32:15 +0000 (22:32 +0100)]
Merge branch 'arm/drivers' into for-next
* arm/drivers: (24 commits)
firmware: xilinx: check return value of zynqmp_pm_get_api_version()
soc: xilinx: add a to_zynqmp_pm_domain macro
soc: xilinx: use a properly named field instead of flags
soc: xilinx: cleanup debug and error messages
soc: xilinx: move PM_INIT_FINALIZE to zynqmp_pm_domains driver
soc: apple: Add driver for Apple PMGR power state controls
soc: renesas: Consolidate product register handling
optee: Fix NULL but dereferenced coccicheck error
memory: renesas-rpc-if: refactor MOIIO and IOFV macros
memory: renesas-rpc-if: avoid use of undocumented bits
memory: renesas-rpc-if: simplify register update
memory: renesas-rpc-if: Silence clang warning
optee: add asynchronous notifications
optee: separate notification functions
tee: export teedev_open() and teedev_close_context()
tee: fix put order in teedev_close_context()
dt-bindings: arm: optee: add interrupt property
docs: staging/tee.rst: add a section on OP-TEE notifications
memory: renesas-rpc-if: Add support for RZ/G2L
memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro
...
Arnd Bergmann [Tue, 14 Dec 2021 21:32:11 +0000 (22:32 +0100)]
Merge branch 'arm/soc' into for-next
* arm/soc:
ARM: shmobile: rcar-gen2: Add missing of_node_put()
Arnd Bergmann [Tue, 14 Dec 2021 21:32:07 +0000 (22:32 +0100)]
Merge branch 'arm/dt' into for-next
* arm/dt:
ARM: dts: ixp4xx: Add devicetree for Gateway 7001
ARM: dts: Add Goramo MultiLink device tree
ARM: dts: Add FSG3 system controller and LEDs
Arnd Bergmann [Tue, 14 Dec 2021 21:32:04 +0000 (22:32 +0100)]
Merge branch 'arm/defconfig' into for-next
* arm/defconfig:
ARM: configs: gemini: Activate crypto driver
Linus Walleij [Mon, 6 Dec 2021 01:11:58 +0000 (02:11 +0100)]
ARM: configs: gemini: Activate crypto driver
This enables the SL3516 crypto driver on the Gemini platforms
where it is available, by default in the defconfig. Clean
up some noise around the crypto options while we're at it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Corentin Labbe <clabbe@baylibre.com>
Link: https://lore.kernel.org/r/20211206011158.4180141-1-linus.walleij@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 14 Dec 2021 16:18:42 +0000 (17:18 +0100)]
Merge tag 'renesas-arm-soc-for-v5.17-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/soc
Renesas ARM SoC updates for v5.17
- Add a missing of_node_put().
* tag 'renesas-arm-soc-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: shmobile: rcar-gen2: Add missing of_node_put()
Link: https://lore.kernel.org/r/cover.1638530611.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 14 Dec 2021 14:54:19 +0000 (15:54 +0100)]
Merge tag 'memory-controller-drv-renesas-5.17' of git://git./linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.17 - Renesas
Changes to the Renesas RPC-IF driver:
1. Add support for R9A07G044 / RZ/G2L.
2. Several minor fixes and improvements to the driver.
* tag 'memory-controller-drv-renesas-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: renesas-rpc-if: refactor MOIIO and IOFV macros
memory: renesas-rpc-if: avoid use of undocumented bits
memory: renesas-rpc-if: simplify register update
memory: renesas-rpc-if: Silence clang warning
memory: renesas-rpc-if: Add support for RZ/G2L
memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro
memory: renesas-rpc-if: Return error in case devm_ioremap_resource() fails
dt-bindings: memory: renesas,rpc-if: Add optional interrupts property
dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044
Link: https://lore.kernel.org/r/20211213105618.5686-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Biju Das [Wed, 8 Dec 2021 14:27:29 +0000 (14:27 +0000)]
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 8 Dec 2021 14:27:28 +0000 (14:27 +0000)]
arm64: dts: renesas: r9a07g044: Add TSU node
Add TSU node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kieran Bingham [Tue, 30 Nov 2021 16:43:11 +0000 (16:43 +0000)]
arm64: dts: renesas: falcon-cpu: Add DSI display output
Provide the display output using the sn65dsi86 MIPI DSI bridge.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20211130164311.2909616-3-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
projects / linux-2.6-block.git / log