Arnd Bergmann [Thu, 21 May 2020 20:49:06 +0000 (22:49 +0200)]
Merge tag 'at91-5.8-dt' of git://git./linux/kernel/git/at91/linux into arm/dt
AT91 DT for 5.8
- New board: Microchip SAMA5D2 Industrial Connectivity Platform
- All SoCs are now converted to the new PMC device tree binding
- sama5d2 flexcom nodes are now fully described in sama5d2.dtsi
* tag 'at91-5.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: (35 commits)
ARM: dts: at91: sama5d2_xplained: Add aliases for the dedicated I2C IPs
ARM: dts: at91: Configure I2C SCL gpio as open drain
ARM: dts: at91: sama5d2_xplained: Describe the flx0 I2C function
ARM: dts: at91: sama5d2_ptc_ek: Add comments to describe the aliases
ARM: dts: at91: sama5d2_xplained: Add alias for DBGU
ARM: dts: at91: sama5d2: Add missing flexcom definitions
ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsi
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functions
ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C function
ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI function
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functions
ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UART
ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsi
ARM: dts: at91: sama5d2: Fix the label numbering for flexcom functions
ARM: dts: at91: sama5d27_wlsom1: Add alias for i2c0
ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP
...
Link: https://lore.kernel.org/r/20200518212844.GA26356@piout.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:48:15 +0000 (22:48 +0200)]
Merge tag 'uniphier-dt64-v5.8' of git://git./linux/kernel/git/masahiroy/linux-uniphier into arm/dt
UniPhier ARM64 SoC DT updates for v5.8
- add DMA controller nodes
- add Akebi96 board support
* tag 'uniphier-dt64-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: Add support for Akebi96
dt-bindings: arm: Add Akebi96 board support
arm64: dts: uniphier: add #address-cells and #size-cells to SPI nodes
arm64: dts: uniphier: Stabilize Ethernet RGMII mode of PXs3 ref board
arm64: dts: uniphier: Add ethernet aliases
arm64: dts: uniphier: Add XDMAC node
Link: https://lore.kernel.org/r/CAK7LNARUL52pBhg8AD9XeScVqhD8qr2eVEfu4+1v8D+KPyOwNw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:47:19 +0000 (22:47 +0200)]
Merge tag 'uniphier-dt-v5.8' of git://git./linux/kernel/git/masahiroy/linux-uniphier into arm/dt
UniPhier ARM SoC DT updates for v5.8
- add DMA controller nodes
* tag 'uniphier-dt-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
ARM: dts: uniphier: add #address-cells and #size-cells to SPI nodes
ARM: dts: uniphier: Add ethernet aliases
ARM: dts: uniphier: Add XDMAC node
Link: https://lore.kernel.org/r/CAK7LNAQXSpg4s0e0d-tp9j85Sj01t13zAa5+rqsOWu4ZvkpYhg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:41:59 +0000 (22:41 +0200)]
Merge tag 'v5.7-next-dts64' of git://git./linux/kernel/git/matthias.bgg/linux into arm/dt
MT2712:
- replace deprecated compatible for the usb PHY
MT6797:
- switch to SPDX identifier
- add and enable I2C device for x20 development board
- add I2C compatible to the binding description
MT7622:
- add Wi-Fi device and enable it for the Bananpi-R64
MT8173:
- add CPU capacities based on Dhryston benchmark
- fix DT build warnings
- set throtteling range to limitless
- add Elm and Hana devices on which several chromebooks are based
- add Global Command Queue entries to the users
MT8183:
- split cpuidle states in two as the clusters have different target residencies
* tag 'v5.7-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: dts: mt8173: Add capacity-dmips-mhz attributes
arm64: dts: mt2712: use non-empty ranges for usb-phy
arm64: dts: mt8173: fix mdp aliases property name
arm64: dts: mediatek: Switch to SPDX license identifier for MT6797 SoC
arm64: dts: mediatek: Enable I2C support for 96Boards X20 Development board
arm64: dts: mediatek: Add I2C support for MT6797 SoC
dt-bindings: i2c: Document I2C controller binding for MT6797 SoC
arm64: dts: mt8173: fix cooling device range
arm64: dts: mediatek: add mt8173 elm and hana board
arm64: dts: mt8173: fix unit name warnings
arm64: dts: mt8173: add uart aliases
dt-bindings: arm64: dts: mediatek: Add mt8173 elm and hana
arm64: dts: mt8183: adjust cpuidle target residency
arm64: dts: mt8173: Add gce setting in mmsys and display node
arm64: dts: mt7622: add built-in Wi-Fi device nodes
Link: https://lore.kernel.org/r/2794a8db-c14f-ac34-9e28-9f3700db6c4c@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:41:15 +0000 (22:41 +0200)]
Merge tag 'ux500-dts-v5.8' of git://git./linux/kernel/git/linusw/linux-stericsson into arm/dt
Ux500 DTS updates for the v5.8 kernel series:
- Add proximity sensor and magnetometer to the Samsung Golden
devicetree.
- Add magnetometer and touchscreen to the Samsung Skomer
devicetree.
* tag 'ux500-dts-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: ux500: Add touchscreen to the Skomer
ARM: dts: ux500: samsung-skomer: Add magnetometer
ARM: dts: ux500: samsung-golden: Add magnetometer
ARM: dts: ux500: samsung-golden: Add proximity sensor
Link: https://lore.kernel.org/r/CACRpkdbukO33SxAZ_yn-1N8=hq3hF5OBOtP_V0fbjRT-fAa87A@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:40:27 +0000 (22:40 +0200)]
Merge tag 'v5.7-next-dts32' of git://git./linux/kernel/git/matthias.bgg/linux into arm/dt
MT2701:
- add MUSB device to the SoC and the EVB
MT7623:
- add Mali-450 device node and bindings
- add phy to gmac2
* tag 'v5.7-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm: dts: mt2701: Add usb2 device nodes
dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible
arm: dts: mt7623: add Mali-450 device node
arm: dts: mt7623: add phy-mode property for gmac2
Link: https://lore.kernel.org/r/ec17cf62-5463-9537-6618-2db9b2b5036e@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:39:46 +0000 (22:39 +0200)]
Merge tag 'socfpga_dts_update_for_v5.8' of git://git./linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.8
- Leave the FPGA bridges disabled in base dtsi
- Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi
* tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges
ARM: dts: socfgpa: set bridges status to disabled
Link: https://lore.kernel.org/r/20200515193029.11318-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:35:34 +0000 (22:35 +0200)]
Merge tag 'sunxi-dt-for-5.8-1' of git://git./linux/kernel/git/sunxi/linux into arm/dt
Our usual number of patches to improve the Allwinner Device Tree
support, including:
- Support for the IOMMU on the H6
- Support for cpufreq / thermal throttling on the H6
- Support for the mailbox on the A64, A83t, H3, H5 and H6
- New boards: A20-OLinuXino-LIME-eMMC
* tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (23 commits)
arm64: dts: allwinner: h6: Add IOMMU
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: h6: add voltage range to OPP table
arm64: dts: allwinner: sun50i-a64: Add missing address/size-cells
arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64
arm64: dts: allwinner: Sort Pine H64 device-tree nodes
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add clock to CPU cores
arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo module
arm64: dts: allwinner: h6: orangepi: Disable OTG mode
arm64: dts: allwinner: h6: orangepi: Add gpio power supply
ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity
arm64: dts: allwinner: h6: Add msgbox node
arm64: dts: allwinner: a64: Add msgbox node
ARM: dts: sunxi: h3/h5: Add msgbox node
ARM: dts: sunxi: a83t: Add msgbox node
ARM: dts: sun8i-h3: add opp table for mali gpu
...
Link: https://lore.kernel.org/r/cfa66bd9-f74c-4614-9ea5-9ef8546cc571.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:34:59 +0000 (22:34 +0200)]
Merge tag 'tegra-for-5.8-arm-dt' of git://git./linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.8-rc1
This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.
* tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: tegra: Kill off "simple-panel" compatibles
Link: https://lore.kernel.org/r/20200515145311.1580134-11-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:30:18 +0000 (22:30 +0200)]
Merge tag 'tegra-for-5.8-dt-bindings' of git://git./linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.8-rc1
This adds bindings for the CSI TPG clock on Tegra210, moves various
clocks from the clock and reset controller to the PMC where their
controls really are, adds bindings for the external memory controller
and video capture controller on Tegra210, as well as CPU frequency
scaling on Tegra20 and Tegra30.
* tag 'tegra-for-5.8-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
dt-bindings: tegra: Add VI and CSI bindings
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
dt-bindings: clock: tegra: Remove PMC clock IDs
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Link: https://lore.kernel.org/r/20200515145311.1580134-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:03:55 +0000 (16:03 +0200)]
Merge tag 'ti-k3-dt-for-v5.8' of git://git./linux/kernel/git/kristo/linux into arm/dt
Texas Instruments K3 SoC DT updates for v5.8
- Add DSS support for both AM65x and J721e
- Add watchdog support for J721e
- Add EHRPWM support for AM65x
- Add Thermal support for AM65x
* tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries
arm64: dts: ti: k3-am65-main: Add ehrpwm nodes
arm64: dts: ti: am654: Add thermal zones
arm64: dts: ti: am65-wakeup: Add VTM node
arm64: dts: ti: k3-j721e-common-proc-board: add assigned clks for DSS
arm64: dts: ti: k3-j721e-main: Add DSS node
arm64: dts: ti: am654: Add DSS node
Link: https://lore.kernel.org/r/7484d3c9-323f-36a3-f0df-1287586f356d@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:03:21 +0000 (16:03 +0200)]
Merge tag 'renesas-dt-bindings-for-v5.8-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.8 (take two)
- Document support for the RZ/G1H-based iWave RainboW Qseven SOM
(G21M) and board (G21D).
* tag 'renesas-dt-bindings-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
Link: https://lore.kernel.org/r/20200515100547.14671-6-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:02:11 +0000 (16:02 +0200)]
Merge tag 'renesas-arm-dt-for-v5.8-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.8 (take two)
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
Qseven SOM (G21M) and board (G21D),
- Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
Silicon Linux EK874 RZ/G2E evaluation kit.
* tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
ARM: dts: r8a7742: Add GPIO nodes
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
ARM: dts: r8a7742: Add IRQC support
ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
ARM: dts: r8a7742: Initial SoC device tree
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:00:46 +0000 (16:00 +0200)]
Merge tag 'stm32-dt-for-v5.8-1' of git://git./linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.8, round 1
Highlights:
----------
MCU part:
-fix a typo for DAC io-channel-cells on f429 and h743
MPU part:
-Generic:
-Bump tp PSCI 1.0
-Fix a typo for DAC io-channel-cells
-Add M4 pdds for deep sleep mode
-Add I2C fatmode plus support
-Add new Octavio lxa-mc1 board based on OSDMP15x SiP
-Add new Stinger96 board support. It is a 96Boards IoT Extended board
based on stm32mp157a SoC. Some figures: 256MB DDR, 125MB and flash,
Onboard BG96 modem...
-Add IoT Box board support based on stinger96 board + Wifi/BT, CCS811
VOC sensor, 2 digitals microphones ...
-DH:
-Adapt dhcom-som and dhcom-pdk2 dts(i) files to STM32MP15 SoC diversity
-Add GPIO led and GPIO keys support on PDK2 board
-AV96:
-Major rework to support official avenger96 board based on DHCOR SOM.
-Prototype board is no more supported
* tag 'stm32-dt-for-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (58 commits)
ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board
ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2
ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add IoT Box board support
dt-bindings: arm: stm32: Document IoT Box compatible
ARM: dts: stm32: Add Stinger96 board support
dt-bindings: arm: stm32: Document Stinger96 compatible
ARM: dts: stm32: Add missing pinctrl entries for STM32MP15
dt-bindings: Add vendor prefix for Shiratech Solutions
ARM: dts: stm32: Add bindings for SPI2 on AV96
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
ARM: dts: stm32: Add bindings for ADC on AV96
ARM: dts: stm32: Add alternate pinmux for ADC pins
ARM: dts: stm32: Add bindings for FDCAN2 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins
ARM: dts: stm32: Add bindings for FDCAN1 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins
ARM: dts: stm32: Repair I2C2 operation on AV96
ARM: dts: stm32: Add alternate pinmux for I2C2 pins
...
Link: https://lore.kernel.org/r/19160355-364d-170c-7ae2-5ba7f714103f@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:51:39 +0000 (15:51 +0200)]
Merge tag 'samsung-dt-5.8' of git://git./linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.8
1. Add DTS for Exynos4210-based Samsung Galaxy S2 (GT-I9100)
mobile phone,
2. Enable WiFi and Bluetooth in multiple boards,
3. Add new features to S5Pv210-based Aries family of mobile phones
(e.g. Samsung Galaxy S): necessary configuration for suspend, audio
support, USB mux, touch keys, panel, i2c-gpio adapters, FM radio, ADC,
4. Many minor fixes (e.g. GPIO polarity, interrupts).
* tag 'samsung-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (29 commits)
ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boards
ARM: dts: s5pv210: Correct FIMC definitions
ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boards
ARM: dts: s5pv210: Enable ADC on Aries boards
ARM: dts: s5pv210: Add an ADC node
ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards
ARM: dts: s5pv210: Add si470x FM radio to Galaxy S
ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boards
ARM: dts: s5pv210: Add panel support to Aries boards
ARM: dts: s5pv210: Add touchkey support to Aries boards
ARM: dts: s5pv210: Add FSA9480 support to Aries boards
ARM: dts: s5pv210: Add WM8994 support to Aries boards
ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for Aries
ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on Aries
ARM: dts: s5pv210: Correct gpi pinctrl node name
ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy S
ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4G
ARM: dts: s5pv210: Add helper define for sleep gpio config
ARM: dts: exynos: Enable WLAN support for the UniversalC210 board
ARM: dts: exynos: Enable WLAN support for the Rinato board
...
Link: https://lore.kernel.org/r/20200512122922.5700-2-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:45:59 +0000 (15:45 +0200)]
Merge tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for v5.8, please pull the following:
- Nicolas updates the Raspberry Pi 4 board DTS to include the GPIO
controlling power to the SD card, adds support for the vmmc regulator
for the emmc2 controller and finally updates the power management
provider for V3D to use the firmware to solve instabilities.
* tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm283x: Use firmware PM driver for V3D
ARM: dts: bcm2711: Add vmmc regulator in emmc2
ARM: dts: bcm2711: Update expgpio's GPIO labels
Link: https://lore.kernel.org/r/20200511210522.28243-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:43:45 +0000 (15:43 +0200)]
Merge tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for 5.8
- Add pinconf for spi2 and spi3 nodes and increase the drive
strength to achieve the max speed for the Hikey960 board
- Add CTI nodes for the Hikey620 board
* tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi6220: Add CTI options
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Link: https://lore.kernel.org/r/5EBE430E.6090508@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:34:22 +0000 (12:34 +0200)]
Merge tag 'realtek-dt-for-5.8' of git://git./linux/kernel/git/afaerber/linux-realtek into arm/dt
Realtek Arm based SoC DT for v5.8
Add RTD1195, RTD1395 and RTD1619 SoCs as well as Xnano X5 TV box.
Clean up memory nodes and /soc ranges. Factor out r-bus and partition it
into CRT, Iso, Misc, SB2 and SCPU Wrapper blocks.
* tag 'realtek-dt-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: (35 commits)
dt-bindings: reset: rtd1295: Add SB2 reset
arm64: dts: realtek: rtd16xx: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd139x: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd129x: Add SB2 and SCPU Wrapper syscon nodes
ARM: dts: rtd1195: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd16xx: Add CRT syscon node
ARM: dts: rtd1195: Add UART resets
ARM: dts: rtd1195: Add reset nodes
dt-bindings: reset: Add Realtek RTD1195
ARM: dts: rtd1195: Add CRT syscon node
arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon
arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon
arm64: dts: realtek: rtd129x: Introduce CRT, iso and misc syscon
ARM: dts: rtd1195: Introduce iso and misc syscon
arm64: dts: realtek: rtd1295: Add Xnano X5
dt-bindings: arm: realtek: Add Xnano X5
dt-bindings: vendor-prefixes: Add Xnano
arm64: dts: realtek: rtd16xx: Add memory reservations
arm64: dts: realtek: rtd16xx: Carve out boot ROM from memory
arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB
...
Link: https://lore.kernel.org/r/20200510232158.18477-2-afaerber@suse.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:19:04 +0000 (12:19 +0200)]
Merge tag 'aspeed-5.8-devicetree' of git://git./linux/kernel/git/joel/aspeed into arm/dt
ASPEED device tree updates for 5.8
New machines:
- YADRO's ast2500 OpenPower P9 Nicole BMC
- Facebook's ast2500 x86 Yosemite V2 BMC
The AST2600 machines Rainier and Tacoma were fleshed out.
Machines have started describing the GPIO names as userspace attempts
to use the GPIO chardev API.
* tag 'aspeed-5.8-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: (32 commits)
ARM: dts: aspeed: Change KCS nodes to v2 binding
ARM: dts: Aspeed: AST2600: Add XDMA PCI-E root control reset
ARM: dts: aspeed: ast2600: Add XDMA Engine
ARM: dts: aspeed: ast2500: Add XDMA Engine
ARM: dts: aspeed: Adding Facebook Yosemite V2 BMC
ARM: dts: aspeed: Add YADRO Nicole BMC
ARM: dts: aspeed: mihawk: add aliases for i2c
ARM: dts: aspeed: tacoma: Add TPM
ARM: dts: aspeed: tacoma: Enable the second VUART
ARM: dts: aspeed: tacoma: Add iio-hwmon nodes for IIO devices
ARM: dts: aspeed: rainier: Add VGA reserved memory region
ARM: dts: aspeed: rainier: Add gpio line names
ARM: dts: aspeed: tacoma: Add gpio line names
ARM: dts: aspeed: zaius: Add gpio line names
ARM: dts: aspeed: romulus: Add gpio line names
ARM: dts: aspeed: witherspoon: Add gpio line names
ARM: dts: aspeed: ast2600: Set arch timer always-on
ARM: dts: aspeed: tacoma: Add GPIOs for FSI
ARM: dts: aspeed: mihawk: Change the name of leds
ARM: dts: aspeed: rainier: Remove regulators
...
Link: https://lore.kernel.org/r/CACPK8Xd-=XFREvvS-mK_ECyn14y0GPAMyy5BpEEUYfaw4jAgsw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:03:23 +0000 (12:03 +0200)]
Merge tag 'omap-for-v5.8/dt-signed' of git://git./linux/kernel/git/tmlind/linux-omap into arm/dt
DTS changes for omaps for v5.8 merge window
We add support for beaglebone-ai board that's am5729 based devices.
Then we have a series changes to configure more hardware acceletators found
on omap variants. With the recent ti-sysc related changes, we can now better
configure the accelerators with help of the clock framework and reset driver.
So with a series of changes from Suman Anna and Tero Kristo, let's configure
IPUs and DSPs for dra7 devices like beagle-x15. And let's also configure the
missing crypto accelerators for omap5 as those have been missing.
Note that there are still some pending driver related patches to use IPU and
DSP related features with mainline kernel, but those are independent of the
devicetree changes.
Then there is a display related change for am57xx-idk for tc358778 bridge,
and a change to configure the missing clock source for some PWM timers.
* tag 'omap-for-v5.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits)
ARM: OMAP5: Make L4SEC clock domain SWSUP only
ARM: OMAP4: Make L4SEC clock domain SWSUP only
ARM: dts: omap5: add DES crypto accelerator node
ARM: dts: omap5: add SHA crypto accelerator node
ARM: dts: omap5: add aes2 entry
ARM: dts: omap5: add aes1 entry
ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes
ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files
ARM: dts: DRA72x: Add aliases for rproc nodes
ARM: dts: DRA74x: Add aliases for rproc nodes
...
Link: https://lore.kernel.org/r/pull-1588873628-477615@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:55:28 +0000 (11:55 +0200)]
Merge tag 'renesas-dt-bindings-for-v5.8-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.8
- Document System Controller (SYSC) and Reset (RST) support for
RZ/G1H.
* tag 'renesas-dt-bindings-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: reset: rcar-rst: Document r8a7742 reset module
dt-bindings: power: rcar-sysc: Document r8a7742 SYSC binding
Link: https://lore.kernel.org/r/20200430084849.1457-6-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:54:41 +0000 (11:54 +0200)]
Merge tag 'renesas-arm-dt-for-v5.8-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.8
- USB, UART, PWM, and PCIe support for R-Car M3-W+,
- PWM (16-bit Timer Pulse Unit and PWM Timers) support for R-Car M2-W,
- Minor fixes and cleanups.
* tag 'renesas-arm-dt-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Fix IOMMU device node names
ARM: dts: renesas: Fix IOMMU device node names
ARM: dts: shmobile: Update CMT1 compatible values
ARM: dts: r8a7791: Add PWM device nodes
ARM: dts: r8a7791: Add TPU device node
arm64: dts: renesas: r8a77961: Add PCIe device nodes
arm64: dts: renesas: r8a77961: Add PWM device nodes
arm64: dts: renesas: r8a77961: Add SCIF and HSCIF nodes
arm64: dts: renesas: r8a77961: Add USB3.0 device nodes
arm64: dts: renesas: r8a77961: Add USB2.0 device nodes
Link: https://lore.kernel.org/r/20200430084849.1457-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:53:19 +0000 (11:53 +0200)]
Merge tag 'versatile-dts-v5.8-1' of git://git./linux/kernel/git/linusw/linux-integrator into arm/dt
Versatile DTS updates for the v5.8 kernel:
Create a new device tree for the Integrator/AP with the
IM-PD1 expansion module fitted in the first slot.
If we want to augment the slot where it is sitting, we can
alter the device tree or make the bootloader do so.
* tag 'versatile-dts-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Add devicetree for Integrator/AP with IM-PD1
Link: https://lore.kernel.org/r/CACRpkdZ-28o+pPdP7i_fc+7g4ndPWf+SWTsjnhFEegTggiXVSg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:51:28 +0000 (11:51 +0200)]
Merge tag 'sti-dt-for-v5.8-round1' of git://git./linux/kernel/git/pchotard/sti into arm/dt
STi DT fixes:
- Remove duplicated rng node in stih407-family.dtsi
- Fix complain about IRQ_TYPE_NONE usage in stih418.dtsi
* tag 'sti-dt-for-v5.8-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
dts: arm: stih407-family: remove duplicated rng nodes
dts: arm: stih418: Fix complain about IRQ_TYPE_NONE usage
Link: https://lore.kernel.org/r/4b0c02e7-a247-50c0-d729-88d16b9dd7fd@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Chunyan Zhang [Tue, 14 Apr 2020 10:16:36 +0000 (18:16 +0800)]
arm64: dts: Add SC9863A emmc and sd card nodes
Add emmc and sd card devicetree nodes for SC9863A.
Link: https://lore.kernel.org/r/20200414101636.24503-3-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Chunyan Zhang [Tue, 14 Apr 2020 10:16:35 +0000 (18:16 +0800)]
arm64: dts: Add SC9863A clock nodes
add clock devicetree nodes for SC9863A.
Link: https://lore.kernel.org/r/20200414101636.24503-2-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tudor Ambarus [Mon, 18 May 2020 11:49:21 +0000 (11:49 +0000)]
ARM: dts: at91: sama5d2_xplained: Add aliases for the dedicated I2C IPs
The sama5d2 SoC has two dedicated I2C IPs that are enabled on
sama5d2_xplained. Add alias for the i2c devices to not rely on
probe order for the i2c device numbering.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200518114802.253660-1-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Linus Walleij [Sat, 16 May 2020 21:29:13 +0000 (23:29 +0200)]
ARM: dts: ux500: Add touchscreen to the Skomer
This adds touchscreen support to the Ux500 Samsung
GT-S7710 "Skomer" mobile phone.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200516212913.485365-1-linus.walleij@linaro.org
Min Guo [Wed, 11 Dec 2019 01:54:42 +0000 (09:54 +0800)]
arm: dts: mt2701: Add usb2 device nodes
Add musb nodes and usb2 phy nodes for MT2701
Signed-off-by: Min Guo <min.guo@mediatek.com>
Link: https://lore.kernel.org/r/20191211015446.11477-3-min.guo@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Sean Wang [Wed, 24 Jul 2019 09:01:00 +0000 (17:01 +0800)]
dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible
The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it
and define its own vendor-specific properties.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/efeadefe3895bcadf1d2e9847b82206dd8c7ec35.1563867856.git.ryder.lee@mediatek.com
[mb: move to yaml file]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Ryder Lee [Wed, 24 Jul 2019 09:00:59 +0000 (17:00 +0800)]
arm: dts: mt7623: add Mali-450 device node
Add a node for Mali-450.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Ulrich Hecht [Fri, 19 Jul 2019 09:50:16 +0000 (11:50 +0200)]
arm64: dts: mt8173: Add capacity-dmips-mhz attributes
Dhrystone benchmark on Acer Chromebook R13 CB5-312T:
A72:
15698587 dps @ 1807 MHz
A53:
7598784 dps @ 1703 MHz
Signed-off-by: Ulrich Hecht <uli-qwV78thtvt0@public.gmane.org>
Link: https://lore.kernel.org/r/1563529816-3992-1-git-send-email-uli@fpond.eu
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Chunfeng Yun [Tue, 11 Feb 2020 03:21:16 +0000 (11:21 +0800)]
arm64: dts: mt2712: use non-empty ranges for usb-phy
Use non-empty ranges for usb-phy to make the layout of
its registers clearer;
Replace deprecated compatible by generic
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Hsin-Yi Wang [Tue, 14 Apr 2020 03:08:14 +0000 (11:08 +0800)]
arm64: dts: mt8173: fix mdp aliases property name
Fix warning:
Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-'
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20200414030815.192104-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Manivannan Sadhasivam [Sat, 22 Feb 2020 16:24:44 +0000 (21:54 +0530)]
arm64: dts: mediatek: Switch to SPDX license identifier for MT6797 SoC
Switch to SPDX license identifier for MT6797 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200222162444.11590-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Manivannan Sadhasivam [Sat, 22 Feb 2020 16:24:43 +0000 (21:54 +0530)]
arm64: dts: mediatek: Enable I2C support for 96Boards X20 Development board
There are 7 I2C ports used on this board. Hence, enable all of them.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200222162444.11590-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Manivannan Sadhasivam [Sat, 22 Feb 2020 16:24:42 +0000 (21:54 +0530)]
arm64: dts: mediatek: Add I2C support for MT6797 SoC
Add I2C support for Mediatek MT6797 SoC. There are a total of 8 I2C
controllers in this SoC (2 being shared) and they are same as the
controllers present in MT6577 SoC. Hence, the driver support is added with
DT fallback method.
As per the datasheet, there are controllers with _imm prefix like i2c2_imm
and i2c3_imm. These appears to be in different memory regions but sharing
the same pins with i2c2 and i2c3 respectively. Since there is no clear
evidence of what they really are, I've adapted the numbering/naming scheme
from the downstream code by Mediatek.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200222162444.11590-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Manivannan Sadhasivam [Sat, 22 Feb 2020 16:24:41 +0000 (21:54 +0530)]
dt-bindings: i2c: Document I2C controller binding for MT6797 SoC
I2C controller driver for MT6577 SoC is reused for MT6797 SoC. Hence,
document that in DT binding.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Wolfram Sang <wsa@kernel.org>
Link: https://lore.kernel.org/r/20200222162444.11590-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Codrin Ciubotariu [Fri, 15 May 2020 14:00:01 +0000 (17:00 +0300)]
ARM: dts: at91: Configure I2C SCL gpio as open drain
The SCL gpio pin used by I2C bus for recovery needs to be configured as
open drain.
Fixes:
455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl")
Fixes:
a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl")
Fixes:
8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20200515140001.287932-1-codrin.ciubotariu@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Michael Kao [Fri, 24 Apr 2020 08:23:40 +0000 (16:23 +0800)]
arm64: dts: mt8173: fix cooling device range
When thermal reaches target temperature,it would be pinned to state 0
(max frequency and power).
Fix the throttling range to no limit.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: Michael Kao <michael.kao@mediatek.com>
Link: https://lore.kernel.org/r/20200424082340.4127-1-michael.kao@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:17 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2_xplained: Describe the flx0 I2C function
Users can choose which flexcom function to use. Describe the I2C
Flexcom0 function. Add alias for the i2c2 node in order to not rely
on probe order for the i2c device numbering. The sama5d2 SoC has
two dedicated i2c buses and five flexcoms that can function as i2c.
The i2c0 and i2c1 aliases are kept for the dedicated i2c buses,
the i2c flexcom functions can be numbered in order starting from i2c2.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-16-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:17 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2_ptc_ek: Add comments to describe the aliases
Indicate which i2c alias is for which connector on the board.
Specify that serial0 is for DBGU. This eases tester's life.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-17-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:16 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2_xplained: Add alias for DBGU
The aliases should be defined in the board dts rather than in the
SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define
the alias for the Serial DBGU in the board dts file. sama5d2 boards use
the "serial0" alias for the Serial DBGU, do the same for sama5d2_xplained.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-15-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:15 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Add missing flexcom definitions
Describe all the flexcom functions for all the flexcom nodes.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-13-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:15 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsi
Device aliases are board-specific, if needed one should define them
in board dts rather than in the SoC dtsi. If an alias from the SoC
dtsi is addressed by a driver that does not use any of the of_alias*()
methods, we can drop it. This is the case for the i2s aliases, drop
them. tcb aliases point to nodes that are not enabled in any of the
sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any
board using that alias is already broken, so get rid of the tcb aliases
too.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:14 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functions
Spare boards of duplicating the DMA bindings. Describe the flx0
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:13 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C function
Spare boards of duplicating the DMA bindings. Describe the flx1
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:12 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI function
Spare boards of duplicating the DMA bindings. Describe the flx3
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:12 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functions
Spare boards of duplicating the DMA bindings. Describe the flx4
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:11 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UART
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs.
Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:10 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsi
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
There is a single functional change in this patch. With the move of the
flx0 uart5 definition in the SoC dtsi, the uart5 from
at91-sama5d27_wlsom1_ek.dts inherits the following optional property:
atmel,fifo-size = <32>;
This particular change was tested by Codrin.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:09 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsi
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:08 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsi
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:08 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsi
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:07 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsi
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tudor Ambarus [Thu, 14 May 2020 05:03:07 +0000 (05:03 +0000)]
ARM: dts: at91: sama5d2: Fix the label numbering for flexcom functions
The sama5d2 SoC has the following IPs: [uart0, uart4], {spi0, spi1}, {i2c0, i2c1}.
Label the flexcom functions in order:
flx0: uart5, spi2, i2c2
flx1: uart6, spi3, i2c3
flx2: uart7, spi4, i2c4
flx3: uart8, spi5, i2c5
flx4: uart9, spi6, i2c6
Some boards respected this scheme, others not. Fix the ones that didn't.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-2-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Lad Prabhakar [Sun, 3 May 2020 21:46:52 +0000 (22:46 +0100)]
dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings,
listing it as a supported board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Sun, 3 May 2020 21:46:51 +0000 (22:46 +0100)]
dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings,
listing it as a supported system on module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Maxime Ripard [Sun, 12 Jan 2020 07:51:46 +0000 (08:51 +0100)]
arm64: dts: allwinner: h6: Add IOMMU
Now that we have a driver for the IOMMU, let's start using it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Marek Vasut [Wed, 13 May 2020 18:10:20 +0000 (20:10 +0200)]
ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an Avenger96 reference board. The DHCOR SoM can be populated with any
STM32MP15xx. Split the DTs to reflect this such that the common SoM and
Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example
implementation of STM32MP157A SoM and Avenger96 board is separated into
stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for
the sake of backward naming compatibility.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:19 +0000 (20:10 +0200)]
ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx
variant. Split the SoC-independent parts of the SoM and PDK2 into the
stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example
of adding STM32MP157C variant of the SoM into a PDK2 carrier board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:18 +0000 (20:10 +0200)]
ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5
GPIO-E may conflict with touchscreen interrupt, hence LED5 must be
disabled when using the DH 560-200 display unit with touchscreen.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:17 +0000 (20:10 +0200)]
ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1
key is polled because it's IRQ line conflicts with ethernet IRQ, the
rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake
up sources.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:15 +0000 (21:12 +0530)]
ARM: dts: stm32: Add IoT Box board support
IoT Box is an IoT gateway device based on Stinger96 board powered by
STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This
device makes use of Stinger96 board by having it as a base board with
one additional mezzanine on top.
Following are the features exposed by this device in addition to the
Stinger96 board:
* WiFi/BT
* CCS811 VOC sensor
* 2x Digital microphones IM69D130
* 12x WS2812B LEDs
Following peripherals are tested and known to work:
* WiFi/BT
* CCS811
More information about this device can be found in Shiratech website:
https://www.shiratech-solutions.com/products/iot-box/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:14 +0000 (21:12 +0530)]
dt-bindings: arm: stm32: Document IoT Box compatible
Document devicetree compatible of Shiratech IoT Box.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:13 +0000 (21:12 +0530)]
ARM: dts: stm32: Add Stinger96 board support
Stinger96 is a 96Boards IoT Extended edition board designed and
manufactured by Shiratech solutions based on STM32MP1 SoC. Following
are the features of this board:
* 256MB DDR
* 125MB NAND Flash
* Onboard BG96 modem
* 1x uSD
* 2x USB (1 available as external connector and another connected to BG96)
* 1x SPI
* 1x PCM
* 2x UART (apart from serial console)
* 2x I2C (apart from one connected to PMIC)
Following peripherals are tested and known to work:
* BG96 modem
* 1x I2C (LS-I2C0)
* 1x SPI
* 1x UART (LS-UART0)
* USB (Only Gadget mode)
* uSD
More information about this board can be found in Shiratech website:
https://www.shiratech-solutions.com/products/stinger96/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:12 +0000 (21:12 +0530)]
dt-bindings: arm: stm32: Document Stinger96 compatible
Document devicetree compatible of Shiratech Stinger96 board.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:11 +0000 (21:12 +0530)]
ARM: dts: stm32: Add missing pinctrl entries for STM32MP15
These pinctrl definitions will be used by Stinger96/IoTBox boards
from Shiratech.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:10 +0000 (21:12 +0530)]
dt-bindings: Add vendor prefix for Shiratech Solutions
This commit adds devicetree vendor prefix for Shiratech solutions,
a SOM/embedded board manufacturing company.
https://www.shiratech-solutions.com/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Clément Péron [Fri, 8 May 2020 19:10:35 +0000 (21:10 +0200)]
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
Enable CPU opp tables for Tanix TX6.
Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.
This voltage has been found using a voltmeter and could be wrong.
Tested-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Clément Péron [Fri, 8 May 2020 19:10:34 +0000 (21:10 +0200)]
arm64: dts: allwinner: h6: add voltage range to OPP table
Some boards have a fixed regulator and can't reach the voltage set
by the OPP table.
Add a range where the minimal voltage is the target and the maximal
voltage is 1.2V.
Suggested-by: Ondřej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Thierry Reding [Fri, 7 Jun 2019 13:58:34 +0000 (15:58 +0200)]
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
The Tegra210 features an instance of the Tegra I2C controller that is
part of the host1x domain and typically used for camera use-cases. It
uses pretty much the same programming model but the registers are laid
out differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 5 May 2020 02:31:56 +0000 (19:31 -0700)]
dt-bindings: tegra: Add VI and CSI bindings
Tegra contains VI controller which can support up to 6 MIPI CSI
camera sensors.
Each Tegra CSI port from CSI unit can be one-to-one mapper to
VI channel and can capture from an external camera sensor or
from built-in test pattern generator.
This patch adds dt-bindings for Tegra VI and CSI.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:25 +0000 (22:02 +0300)]
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
Add device-tree binding that describes CPU frequency-scaling hardware
found on NVIDIA Tegra20/30 SoCs.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Wed, 29 May 2019 08:21:32 +0000 (16:21 +0800)]
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
Add the binding document for the external memory controller (EMC) which
communicates with external LPDDR4 devices. It includes the bindings of
the EMC node and a sub-node of EMC table which under the reserved memory
node. The EMC table contains the data of the rates that EMC supported.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 14 Jan 2020 07:24:26 +0000 (23:24 -0800)]
dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 5 May 2020 02:31:54 +0000 (19:31 -0700)]
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lad Prabhakar [Mon, 20 Apr 2020 15:49:54 +0000 (16:49 +0100)]
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
This patch adds support for AISTARVISION MIPI Adapter V2.1 board connected
to G2E board. Common file aistarvision-mipi-adapter-2.1.dtsi is created
which have the camera endpoint nodes for imx219 and ov5645 so that this can
be re-used with other G2x platforms.
r8a774c0-ek874-mipi-2.1.dts file enables the required VIN/CSI nodes and by
default ties ov5645 camera endpoint to CSI2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1587397794-11237-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:35 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add GPIO nodes
Describe GPIO blocks in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588794695-27852-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:33 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
Describe [H]SCIF{A|B} ports in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588794695-27852-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:29 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add IRQC support
Describe the IRQC interrupt controller in the r8a7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Marek Vasut [Wed, 29 Apr 2020 16:37:41 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for SPI2 on AV96
Add SPI2 bindings to AV96 DT, the SPI2 IOs are present on
low-speed expansion connector X6. This is disabled by default
and can be enabled if something is connected there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:40 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
Add another mux option for SPI2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:39 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for ADC on AV96
Add ADC bindings to AV96 DT, the ADC inputs are present on
low-speed expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:38 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for ADC pins
Add another mux option for ADC pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:37 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for FDCAN2 on AV96
Add FDCAN2 bindings to AV96 DT, the FDCAN2 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:36 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins
Add another mux option for FDCAN2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:35 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for FDCAN1 on AV96
Add FDCAN1 bindings to AV96 DT, the FDCAN1 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:34 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins
Add another mux option for FDCAN1 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:33 +0000 (18:37 +0200)]
ARM: dts: stm32: Repair I2C2 operation on AV96
The I2C2 uses different pinmux on AV96, use correct pinmux and
also add comments about the I2C being present on the "low-speed"
expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:32 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for I2C2 pins
Add another mux option for I2C2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Etienne Carriere [Wed, 6 May 2020 17:48:40 +0000 (19:48 +0200)]
ARM: dts: stm32: bump PSCI to version 1.0 on stm32mp15x
Declare PSCI v1.0 support instead of v0.1 as the former is supported
by the PSCI firmware stacks stm32mp15x relies on.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Mike Leach [Wed, 15 Apr 2020 20:12:59 +0000 (21:12 +0100)]
arm64: dts: hi6220: Add CTI options
Adds in CTI device tree information for the Hikey620 board.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Loic Poulain [Tue, 24 Mar 2020 10:07:52 +0000 (11:07 +0100)]
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Only the pinmux was selected, not the pinconf, leading to spi issues.
Increase drive strength so that max speed (25Mhz) can be achieved.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:29 +0000 (22:02 +0300)]
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:28 +0000 (22:02 +0300)]
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
Set min/max voltage and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:02 +0000 (17:30 +0300)]
ARM: OMAP5: Make L4SEC clock domain SWSUP only
Commit
c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:01 +0000 (17:30 +0300)]
ARM: OMAP4: Make L4SEC clock domain SWSUP only
Commit
c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP4, so do the same change
for OMAP4 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:00 +0000 (17:30 +0300)]
ARM: dts: omap5: add DES crypto accelerator node
OMAP5 contains a single DES crypto accelerator instance. Add node for
this in DT to enable it.
We keep the node disabled for now, as it appears OMAP5 platform is
running out of available DMA channels, and DES is the least interesting
crypto accelerator available on the device.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:29:59 +0000 (17:29 +0300)]
ARM: dts: omap5: add SHA crypto accelerator node
Add the single available SHA crypto accelerator device for OMAP5 SoC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
projects / linux-block.git / log