Stephen Boyd [Fri, 12 Jul 2019 18:11:30 +0000 (11:11 -0700)]
Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'clk-sprd' and 'clk-at91' into clk-next
- Support for CPU clks on Raspberry Pi devices
- Slow clk support for AT91 SAM9X60 SoCs
* clk-rpi-cpufreq:
clk: raspberrypi: register platform device for raspberrypi-cpufreq
firmware: raspberrypi: register clk device
clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
clk: bcm2835: remove pllb
* clk-tegra:
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
clk: tegra: Warn if an enabled PLL is in IDDQ
clk: tegra: Do not warn unnecessarily
clk: tegra210: fix PLLU and PLLU_OUT1
* clk-simplify-provider.h:
clk: consoldiate the __clk_get_hw() declarations
clk: Unexport __clk_of_table
clk: Remove ifdef for COMMON_CLK in clk-provider.h
* clk-sprd:
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: sprd: Check error only for devm_regmap_init_mmio()
clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
* clk-at91:
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: at91: sckc: add support for SAM9X60
dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
clk: at91: sckc: add support to specify registers bit offsets
clk: at91: sckc: sama5d4 has no bypass support
Stephen Boyd [Fri, 12 Jul 2019 18:11:16 +0000 (11:11 -0700)]
Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' into clk-next
- Add a 'clk_parent' file in clk debugfs
- Remove dead code in various clk drivers
* clk-debugfs:
clk: Add clk_parent entry in debugfs
* clk-unused:
clk: qcom: Fix -Wunused-const-variable
clk: mmp: frac: Remove set but not used variable 'prev_rate'
clk: ti: Remove unused functions
clk: mediatek: mt8516: Remove unused variable
* clk-refactor:
clk: clk-
cdce706: simplify getting the adapter of a client
clk: Simplify clk_core_can_round()
* clk-qoriq:
clk: qoriq: add support for lx2160a
Stephen Boyd [Fri, 12 Jul 2019 18:11:06 +0000 (11:11 -0700)]
Merge branches 'clk-bulk-optional', 'clk-kirkwood', 'clk-socfpga' and 'clk-docs' into clk-next
- Add a clk_bulk_get_optional() API (with devm too)
- Support for Marvell 98DX1135 SoCs
* clk-bulk-optional:
clk: Document some devm_clk_bulk*() APIs
clk: Add devm_clk_bulk_get_optional() function
clk: Add clk_bulk_get_optional() function
* clk-kirkwood:
clk: kirkwood: Add support for MV98DX1135
dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock
* clk-socfpga:
clk: socfpga: stratix10: fix divider entry for the emac clocks
clk: socfpga: stratix10: add additional clocks needed for the NAND IP
* clk-docs:
clk: Grammar missing "and", Spelling s/statisfied/satisfied/
Stephen Boyd [Fri, 12 Jul 2019 18:10:59 +0000 (11:10 -0700)]
Merge branches 'clk-ti', 'clk-samsung', 'clk-imx' and 'clk-allwinner' into clk-next
* clk-ti:
clk: ti: Use int to check return value from of_property_count_elems_of_size()
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: probe clocks from DT instead of firmware
clk: keystone: sci-clk: split out the fw clock parsing to own function
clk: keystone: sci-clk: cut down the clock name length
* clk-samsung:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
* clk-imx: (38 commits)
clk: imx8mq: Keep uart clocks on during system boot
clk: imx: Remove __init for imx_register_uart_clocks() API
clk: imx6q: fix section mismatch warning
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
clk: imx8mq: Use imx_check_clocks() API directly
clk: imx: Remove __init for imx_check_clocks() API
clk: imx6sll: Switch to clk_hw based API
clk: imx7d: Switch to clk_hw based API
clk: imx6ul: Switch to clk_hw based API
clk: imx6sx: Switch to clk_hw based API
clk: imx6q: Switch to clk_hw based API
clk: imx6sl: Switch to clk_hw based API
clk: imx: Switch wrappers to clk_hw based API
clk: imx: clk-fixup-mux: Switch to clk_hw based API
clk: imx: clk-fixup-div: Switch to clk_hw based API
clk: imx: clk-gate-exclusive: Switch to clk_hw based API
clk: imx: clk-pfd: Switch to clk_hw based API
clk: imx: clk-pllv3: Switch to clk_hw based API
clk: imx: clk-gate2: Switch to clk_hw based API
clk: imx: clk-cpu: Switch to clk_hw based API
...
* clk-allwinner: (29 commits)
clk: Simplify debugfs printing and add a newline
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
...
Stephen Boyd [Fri, 12 Jul 2019 18:10:52 +0000 (11:10 -0700)]
Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next
* clk-qcom-gdsc-warn:
clk: qcom: gdsc: WARN when failing to toggle
* clk-ingenic:
MIPS: Remove dead code
clk: ingenic: Remove unused functions
MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode
clk: ingenic: Handle setting the Low-Power Mode bit
clk: ingenic: Add missing header in cgu.h
clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks
clk: ingenic/jz4770: Fix incorrect dividers for main clocks
clk: ingenic/jz4740: Fix incorrect dividers for main clocks
clk: ingenic: Add support for divider tables
* clk-qcom-qcs404-reset:
clk: gcc-qcs404: Add PCIe resets
* clk-xgene-limit:
clk: xgene: Don't build COMMON_CLK_XGENE by default
* clk-meson:
clk: meson: g12a: mark fclk_div3 as critical
clk: meson: g12a: Add support for G12B CPUB clocks
dt-bindings: clk: meson: add g12b periph clock controller bindings
clk: meson-g12a: add temperature sensor clocks
dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
clk: meson: meson8b: add the cts_i958 clock
clk: meson: meson8b: add the cts_mclk_i958 clocks
clk: meson: meson8b: add the cts_amclk clocks
dt-bindings: clock: meson8b: add the audio clocks
clk: meson: g12a: add controller register init
clk: meson: eeclk: add init regs
clk: meson: g12a: add mpll register init sequences
clk: meson: mpll: add init callback and regs
clk: meson: axg: spread spectrum is on mpll2
clk: meson: gxbb: no spread spectrum on mpll0
clk: meson: mpll: properly handle spread spectrum
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
Stephen Boyd [Fri, 12 Jul 2019 18:10:43 +0000 (11:10 -0700)]
Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next
- Add support to get duty cycle of generic pwm clks
* clk-pwm-duty:
clk: pwm: implement the .get_duty_cycle callback
* clk-bcm:
clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB
clk: bcm: Make BCM2835 clock drivers selectable
* clk-mtk:
clk: mediatek: Remove MT8183 unused clock
clk: mediatek: add audsys clock driver for MT8516
dt-bindings: mediatek: audsys: add support for MT8516
* clk-qcom-msm8998-gpu:
dt-bindings: clock: Document gpucc for msm8998
* clk-renesas:
clk: renesas: cpg-mssr: Use [] to denote a flexible array member
clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
clk: renesas: mstp: Combine group-private and clock array allocation
clk: renesas: div6: Combine clock-private and parent array allocation
clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
clk: renesas: r8a774a1: Add TMU clock
clk: renesas: r8a77995: Add CMM clocks
clk: renesas: r8a77990: Add CMM clocks
clk: renesas: r8a77965: Add CMM clocks
clk: renesas: r8a7795: Add CMM clocks
clk: renesas: r9a06g032: Add clock domain support
dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
clk: renesas: mstp: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
clk: renesas: r8a7796: Add CMM clocks
clk: renesas: r8a779{5|6|65}: Add TPU clock
Stephen Rothwell [Tue, 2 Jul 2019 02:03:50 +0000 (12:03 +1000)]
clk: consoldiate the __clk_get_hw() declarations
Without this we were getting errors like:
In file included from drivers/clk/clkdev.c:22:0:
drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration
include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here
Fixes:
59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h")
fixes:
73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunyan Zhang [Wed, 22 May 2019 01:15:03 +0000 (09:15 +0800)]
clk: sprd: Add check for return value of sprd_clk_regmap_init()
sprd_clk_regmap_init() doesn't always return success, adding check
for its return value should make the code more strong.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
[sboyd@kernel.org: Add a missing int ret]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:45 +0000 (18:53 +0300)]
clk: at91: sckc: use dedicated functions to unregister clock
Use at91 specific functions to free all resources in case of error.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:44 +0000 (18:53 +0300)]
clk: at91: sckc: improve error path for sama5d4 sck registration
Improve error path for sama5d4 sck registration.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:43 +0000 (18:53 +0300)]
clk: at91: sckc: remove unnecessary line
Remove unnecessary line.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:42 +0000 (18:53 +0300)]
clk: at91: sckc: improve error path for sam9x5 sck register
Improve error path for sam9x5 slow clock registration.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:41 +0000 (18:53 +0300)]
clk: at91: sckc: add support to free slow clock osclillator
Add support to free slow clock oscillator resources.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:40 +0000 (18:53 +0300)]
clk: at91: sckc: add support to free slow rc oscillator
Add support to free slow rc oscillator resources.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Thu, 27 Jun 2019 15:53:39 +0000 (18:53 +0300)]
clk: at91: sckc: add support to free slow oscillator
Add support to free slow oscillator resources.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 21 May 2019 10:11:33 +0000 (10:11 +0000)]
clk: at91: sckc: add support for SAM9X60
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 21 May 2019 10:11:29 +0000 (10:11 +0000)]
dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 21 May 2019 10:11:26 +0000 (10:11 +0000)]
clk: at91: sckc: add support to specify registers bit offsets
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 21 May 2019 10:11:22 +0000 (10:11 +0000)]
clk: at91: sckc: sama5d4 has no bypass support
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunyan Zhang [Wed, 22 May 2019 01:15:02 +0000 (09:15 +0800)]
clk: sprd: Check error only for devm_regmap_init_mmio()
The function devm_regmap_init_mmio() wouldn't return NULL pointer for
now, so only need to ensure the return value is not an error code.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunyan Zhang [Wed, 22 May 2019 01:15:01 +0000 (09:15 +0800)]
clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
devm_ioremap_resources() automatically requests resources and devm_ wrappers
do better error handling and unmapping of the I/O region when needed,
that would make drivers more clean and simple.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Thierry Reding [Thu, 13 Jun 2019 16:12:25 +0000 (18:12 +0200)]
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
It turns out that this PLL is not used on Tegra210, so there's no need
to enable it via the init table. Remove the init table entry for this
PLL to avoid it getting enabled at boot time. If the bootloader enabled
it and forgot to turn it off, the common clock framework will now know
to disable it because it is unused.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Thierry Reding [Thu, 13 Jun 2019 16:12:24 +0000 (18:12 +0200)]
clk: tegra: Warn if an enabled PLL is in IDDQ
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
configuration that makes sense, so warn about it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Thierry Reding [Thu, 13 Jun 2019 16:12:23 +0000 (18:12 +0200)]
clk: tegra: Do not warn unnecessarily
There is no need to warn if the reference PLL is enabled with the
correct defaults. Only warn if the boot values don't match the defaults.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
JC Kuo [Wed, 12 Jun 2019 03:14:34 +0000 (11:14 +0800)]
clk: tegra210: fix PLLU and PLLU_OUT1
Full-speed and low-speed USB devices do not work with Tegra210
platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
When full-speed device is connected:
[ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
[ 14.196295] usb 1-3: device descriptor read/64, error -71
[ 14.436311] usb 1-3: device descriptor read/64, error -71
[ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
[ 14.812335] usb 1-3: device descriptor read/64, error -71
[ 15.052316] usb 1-3: device descriptor read/64, error -71
[ 15.164799] usb usb1-port3: attempt power cycle
When low-speed device is connected:
[ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.564977] usb usb1-port3: attempt power cycle
This commit fixes the issue by:
1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
because PLLU_OUT1 is parent of XUSB_FS_SRC.
2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
Reference Manual.
Fixes:
e745f992cf4b ("clk: tegra: Rework pll_u")
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nicolas Saenz Julienne [Wed, 12 Jun 2019 18:24:57 +0000 (20:24 +0200)]
clk: raspberrypi: register platform device for raspberrypi-cpufreq
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be
configured as a module, the cpu clock might not be available for the
cpufreq driver during it's init process. So we register the
'raspberrypi-cpufreq' platform device after the probe sequence succeeds.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nicolas Saenz Julienne [Wed, 12 Jun 2019 18:24:55 +0000 (20:24 +0200)]
firmware: raspberrypi: register clk device
Since clk-raspberrypi is tied to the VC4 firmware instead of particular
hardware it's registration should be performed by the firmware driver.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nicolas Saenz Julienne [Wed, 12 Jun 2019 18:24:54 +0000 (20:24 +0200)]
clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
Raspberry Pi's firmware offers an interface though which update it's
clock's frequencies. This is specially useful in order to change the CPU
clock (pllb_arm) which is 'owned' by the firmware and we're unable to
scale using the register interface provided by clk-bcm2835.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nicolas Saenz Julienne [Wed, 12 Jun 2019 18:24:53 +0000 (20:24 +0200)]
clk: bcm2835: remove pllb
Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vabhav Sharma [Fri, 26 Apr 2019 06:53:38 +0000 (06:53 +0000)]
clk: qoriq: add support for lx2160a
Add clockgen support and configuration for NXP SoC lx2160a
with compatible property as "fsl,lx2160a-clockgen".
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Wolfram Sang [Sat, 8 Jun 2019 10:55:40 +0000 (12:55 +0200)]
clk: clk-
cdce706: simplify getting the adapter of a client
We have a dedicated pointer for that, so use it. Much easier to read and
less computation involved.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nathan Huckleberry [Tue, 11 Jun 2019 21:11:34 +0000 (14:11 -0700)]
clk: qcom: Fix -Wunused-const-variable
Clang produces the following warning
drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable]
static const struct
parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] =
{ ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static
const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^
drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map'
[-Wunused-const-variable] static const struct parent_map
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^
drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div'
[-Wunused-const-variable] static const char * const
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
It looks like these were never used.
Fixes:
b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Cc: clang-built-linux@googlegroups.com
Link: https://github.com/ClangBuiltLinux/linux/issues/518
Suggested-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Tue, 11 Jun 2019 18:07:57 +0000 (20:07 +0200)]
MIPS: Remove dead code
Remove the unused <asm/mach-jz4740/clock.h> include.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Tue, 11 Jun 2019 18:07:56 +0000 (20:07 +0200)]
clk: ingenic: Remove unused functions
These functions are not called anywhere anymore, they can safely be
removed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Tue, 11 Jun 2019 18:07:55 +0000 (20:07 +0200)]
MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode
Instead of forcing the jz4740 clocks to suspend here, we let the CGU
driver handle it.
We also let the CGU driver set the "sleep mode" bit.
This has the added benefit that now it is possible to build a kernel on
SoCs newer than the JZ4740 with CONFIG_PM.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Tue, 11 Jun 2019 18:07:54 +0000 (20:07 +0200)]
clk: ingenic: Handle setting the Low-Power Mode bit
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction
suspend the system.
This is not really clock-related, but this bit happens to be in the
register set of the CGU.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Tue, 11 Jun 2019 18:07:53 +0000 (20:07 +0200)]
clk: ingenic: Add missing header in cgu.h
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw'
structures (no pointers), so the <linux/clk-provider.h> header should be
included.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
[sboyd@kernel.org: Drop removal of includes in drivers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Leonard Crestez [Mon, 10 Jun 2019 11:06:38 +0000 (14:06 +0300)]
clk: Add clk_parent entry in debugfs
This allows to easily determine the parent in shell scripts without
parsing more complex files.
Add the clk_parent file for all clks which can have a parent, not just
muxes. This way it can be used to determine the clk tree structure
without parsing more complex files.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Geert Uytterhoeven [Mon, 17 Jun 2019 13:56:02 +0000 (15:56 +0200)]
clk: Grammar missing "and", Spelling s/statisfied/satisfied/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Geert Uytterhoeven [Mon, 17 Jun 2019 12:02:48 +0000 (14:02 +0200)]
clk: Simplify clk_core_can_round()
A boolean expression already evaluates to true or false, so there is no
need to check the result and return true or false explicitly.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Tue, 25 Jun 2019 13:55:35 +0000 (08:55 -0500)]
clk: socfpga: stratix10: fix divider entry for the emac clocks
The fixed dividers for the emac clocks should be 2 not 4.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Mon, 24 Jun 2019 21:47:10 +0000 (16:47 -0500)]
clk: socfpga: stratix10: add additional clocks needed for the NAND IP
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chris Packham [Mon, 17 Jun 2019 21:54:58 +0000 (09:54 +1200)]
clk: kirkwood: Add support for MV98DX1135
The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except that the core clock speed is fixed to 166Mhz.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chris Packham [Mon, 17 Jun 2019 21:54:56 +0000 (09:54 +1200)]
dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock
Add compatible string for the core clock on the 98dx1135 switch with
integrated CPU.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 25 Jun 2019 21:20:56 +0000 (14:20 -0700)]
clk: Document some devm_clk_bulk*() APIs
Add some new clk devm APIs that we've added over time to the devres
documentation.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Sylwester Nawrocki [Wed, 19 Jun 2019 09:39:26 +0000 (11:39 +0200)]
clk: Add devm_clk_bulk_get_optional() function
Add managed version of the clk_bulk_get_optional() helper function.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@kernel.org: Mark __devm_clk_bulk_get() static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Sylwester Nawrocki [Wed, 19 Jun 2019 09:39:25 +0000 (11:39 +0200)]
clk: Add clk_bulk_get_optional() function
clk_bulk_get_optional() allows to get a group of clocks where one
or more is optional. For a not available clock, e.g. not specifed
in the clock consumer node in DT, its respective struct clk pointer
will be NULL. This allows for operating on a group of returned
clocks (struct clk_bulk_data array) with existing clk_bulk* APIs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 25 Jun 2019 03:01:55 +0000 (20:01 -0700)]
clk: Simplify debugfs printing and add a newline
The possible parent printing function duplicates a bunch of if
conditions. Pull that into another function so we can print an extra
character at the end, either a space or a newline. This way we can add
the required newline that got lost here and also shorten the code.
Fixes:
2d156b78ce8f ("clk: Fix debugfs clk_possible_parents for clks without parent string names")
Cc: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 25 Jun 2019 03:16:13 +0000 (20:16 -0700)]
Merge tag 'imx-clk-5.3' of git://git./linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver changes from Shawn Guo:
- A series from Abel Vesa to switch i.MX6 and i.MX7 clock drivers to
clk_hw based API
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Create a common function imx_mmdc_mask_handshake() for masking MMDC
handshake
- Drop __init for function imx_check_clocks() and imx_register_uart_clocks(),
so that they can be used by i.MX8 clock drivers which use driver model
- Use devm_platform_ioremap_resource() instead of of_iomap() for imx8mq
clock driver
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock.
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
* tag 'imx-clk-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (38 commits)
clk: imx8mq: Keep uart clocks on during system boot
clk: imx: Remove __init for imx_register_uart_clocks() API
clk: imx6q: fix section mismatch warning
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
clk: imx8mq: Use imx_check_clocks() API directly
clk: imx: Remove __init for imx_check_clocks() API
clk: imx6sll: Switch to clk_hw based API
clk: imx7d: Switch to clk_hw based API
clk: imx6ul: Switch to clk_hw based API
clk: imx6sx: Switch to clk_hw based API
clk: imx6q: Switch to clk_hw based API
clk: imx6sl: Switch to clk_hw based API
clk: imx: Switch wrappers to clk_hw based API
clk: imx: clk-fixup-mux: Switch to clk_hw based API
clk: imx: clk-fixup-div: Switch to clk_hw based API
clk: imx: clk-gate-exclusive: Switch to clk_hw based API
clk: imx: clk-pfd: Switch to clk_hw based API
clk: imx: clk-pllv3: Switch to clk_hw based API
clk: imx: clk-gate2: Switch to clk_hw based API
clk: imx: clk-cpu: Switch to clk_hw based API
...
Stephen Boyd [Tue, 25 Jun 2019 03:07:46 +0000 (20:07 -0700)]
Merge tag 'clk-v5.3-samsung' of git://git./linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Addition of clocks required for new Exynos5422 Dynamic Memory
Controller driver
- clock definition for Exynos4412 Mali
- minor clean up of clk-exynos5433.c
* tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
Stephen Boyd [Tue, 25 Jun 2019 03:04:57 +0000 (20:04 -0700)]
Merge tag 'clk-renesas-for-v5.3-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add CMM (Color Management Module) clocks on R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on RZ/G2M
- Small cleanups and fixes
* tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Use [] to denote a flexible array member
clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
clk: renesas: mstp: Combine group-private and clock array allocation
clk: renesas: div6: Combine clock-private and parent array allocation
clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
clk: renesas: r8a774a1: Add TMU clock
clk: renesas: r8a77995: Add CMM clocks
clk: renesas: r8a77990: Add CMM clocks
clk: renesas: r8a77965: Add CMM clocks
clk: renesas: r8a7795: Add CMM clocks
Stephen Boyd [Tue, 25 Jun 2019 01:28:31 +0000 (18:28 -0700)]
Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2
from Chen-Yu Tsai:
"The first part of ongoing work to convert the sunxi-ng clk driver from
using global clock name strings to describe clk parenting, to having
direct struct clk_hw pointers, or local names based on clock-names from
the device tree binding.
This is based on Stephen Boyd's recent work allowing clk drivers to
specify clk parents using struct clk_hw * or parsing DT phandles in the
clk node.
This series can be split into a few major parts:
1) The first patch is a small fix for clk debugfs representation.
2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
situations I encountered, or assume I will encounter, such as single
internal (struct clk_hw *) parent, single DT (struct clk_parent_data
.fw_name), multiple internal parents, and multiple mixed (internal +
DT) parents. A special variant for just an internal single parent is
added, CLK_HW_INIT_HWS, which lets the driver share the singular
list, instead of having the compiler create a compound literal every
time. It might even make sense to only keep this variant.
3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
is the same as the single parent CLK_HW_INIT_* helpers.
4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
either struct clk_hw * or DT .fw_name types, whichever the hardware
requires.
5) The beginning of SUNXI_CCU_GATE conversion to local parent
references. This part is not done. They are included as justification
and examples for the shared list of clk parents case."
* tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits)
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw *
...
Stephen Boyd [Tue, 25 Jun 2019 01:17:28 +0000 (18:17 -0700)]
Merge tag 'sunxi-clk-for-5.3-
201906210814' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
- A few patches to fix two minor bugs
- Introduce a schema for our device tree bindings
* tag 'sunxi-clk-for-5.3-
201906210814' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
dt-bindings: clk: Convert Allwinner CCU to a schema
clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
clk-sunxi: fix a missing-check bug in sunxi_divs_clk_setup()
Stephen Boyd [Tue, 25 Jun 2019 01:06:15 +0000 (18:06 -0700)]
clk: ti: Use int to check return value from of_property_count_elems_of_size()
This function can return a negative number when it fails, but res->sets
is at most a u16 which can't hold that negative number. Let's store the
result into an int, ret, and then assign that to res->sets when it works
to avoid this logical impossibility.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 25 Jun 2019 00:52:29 +0000 (17:52 -0700)]
Merge tag 'keystone-clk-for-5.3-v2' of git://git./linux/kernel/git/kristo/linux into clk-ti
Pull TI Keystone clk driver changes from Tero Kristo:
- Add support for 32 bit clock IDs for sci-clks, this is needed
for the new J721e SoC which has a few devices that have more than
255 clocks associated to them.
- Clock probing done from DT by default instead of firmware side.
Scanning clocks from DT is much faster than firmware, and also we
can omit unnecessary clocks which saves even more time. This has been
done in the interest of saving boot time.
- Remove the device tree node path from the registered sci-clk names.
This mainly makes the debugfs interface more readable.
- Also contains a single drivers/firmware change which needs to go in
via this pull-request; to support the 32bit clock IDs.
* tag 'keystone-clk-for-5.3-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: probe clocks from DT instead of firmware
clk: keystone: sci-clk: split out the fw clock parsing to own function
clk: keystone: sci-clk: cut down the clock name length
Stephen Boyd [Tue, 25 Jun 2019 00:40:40 +0000 (17:40 -0700)]
Merge tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson into clk-meson
Pull Amlogic clk driver updates from Jerome Brunet:
- Fix mpll fractional part and spread sprectrum issues
- Add meson8 audio clocks
- Add g12a temperature sensors clocks
- Add g12a and g12b cpu clocks
* tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson:
clk: meson: g12a: mark fclk_div3 as critical
clk: meson: g12a: Add support for G12B CPUB clocks
dt-bindings: clk: meson: add g12b periph clock controller bindings
clk: meson-g12a: add temperature sensor clocks
dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
clk: meson: meson8b: add the cts_i958 clock
clk: meson: meson8b: add the cts_mclk_i958 clocks
clk: meson: meson8b: add the cts_amclk clocks
dt-bindings: clock: meson8b: add the audio clocks
clk: meson: g12a: add controller register init
clk: meson: eeclk: add init regs
clk: meson: g12a: add mpll register init sequences
clk: meson: mpll: add init callback and regs
clk: meson: axg: spread spectrum is on mpll2
clk: meson: gxbb: no spread spectrum on mpll0
clk: meson: mpll: properly handle spread spectrum
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
Anson Huang [Wed, 19 Jun 2019 07:12:40 +0000 (15:12 +0800)]
clk: imx8mq: Keep uart clocks on during system boot
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Anson Huang [Wed, 19 Jun 2019 07:12:39 +0000 (15:12 +0800)]
clk: imx: Remove __init for imx_register_uart_clocks() API
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_register_uart_clocks() API, so
imx_register_uart_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Chen-Yu Tsai [Fri, 3 May 2019 11:31:04 +0000 (19:31 +0800)]
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS
as the parent clock is internal to this clock unit.
To avoid duplication of clock definitions, we fix up the parent
reference for A83T in the A83T init function.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 11:25:12 +0000 (19:25 +0800)]
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to
specify the parent clock.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 11:21:08 +0000 (19:21 +0800)]
clk: sunxi-ng: gate: Add macros for referencing local clock parents
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw,
and .parent_data, for clk drivers to specify parents using a combination
of device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add four new macros:
- SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead
of a string, as its parent.
- SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry
in the device tree to specify the clock parent.
- SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its
parent. This allows the array to be shared with other clk
declarations.
- SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data *
as its parent. This allows the array to be shared with other clk
declarations.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:10:53 +0000 (18:10 +0800)]
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:10:39 +0000 (18:10 +0800)]
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk
is added as the definitions of the fixed factor clocks appear much later
in the file. The position of fixed factor clock definitions will be
moved for all drivers at a later time, before the conversion of all
other clock types.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:09:33 +0000 (18:09 +0800)]
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:08:46 +0000 (18:08 +0800)]
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Geert Uytterhoeven [Mon, 17 Jun 2019 11:58:58 +0000 (13:58 +0200)]
clk: renesas: cpg-mssr: Use [] to denote a flexible array member
Flexible array members should be denoted using [] instead of [0], else
gcc will not warn when they are no longer at the end of the structure.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 12 Jun 2019 15:27:56 +0000 (17:27 +0200)]
clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
Make cpg_mssr_priv.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the driver-private
structure and array of available clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 12 Jun 2019 15:25:39 +0000 (17:25 +0200)]
clk: renesas: mstp: Combine group-private and clock array allocation
Make mstp_clock_group.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the group-private
structure and array of module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 12 Jun 2019 15:22:18 +0000 (17:22 +0200)]
clk: renesas: div6: Combine clock-private and parent array allocation
Make div6_clock.parents[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the clock-private
structure and array of parent clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 12 Jun 2019 15:19:12 +0000 (17:19 +0200)]
clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
New fields were added, but kerneldoc was forgotten, or inserted at the
wrong place.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Krzysztof Kozlowski [Tue, 18 Jun 2019 19:05:26 +0000 (21:05 +0200)]
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Arnd Bergmann [Mon, 17 Jun 2019 11:11:35 +0000 (13:11 +0200)]
clk: imx6q: fix section mismatch warning
The imx6q_obtain_fixed_clk_hw lacks an __init marker, which
leads to this otherwise harmless warning:
WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw()
The function imx6q_obtain_fixed_clk_hw() references
the function __init imx_obtain_fixed_clock_hw().
This is often because imx6q_obtain_fixed_clk_hw lacks a __init
annotation or the annotation of imx_obtain_fixed_clock_hw is wrong.
Fixes:
992b703b5b38 ("clk: imx6q: Switch to clk_hw based API")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:29:42 +0000 (11:29 +0800)]
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:08:18 +0000 (18:08 +0800)]
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:07:52 +0000 (18:07 +0800)]
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:07:10 +0000 (18:07 +0800)]
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:06:26 +0000 (18:06 +0800)]
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:06:05 +0000 (18:06 +0800)]
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:05:35 +0000 (18:05 +0800)]
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:05:18 +0000 (18:05 +0800)]
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 10:02:31 +0000 (18:02 +0800)]
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:18:24 +0000 (11:18 +0800)]
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.
For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:21:56 +0000 (11:21 +0800)]
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
Commit
89a5ddcc799d ("clk: Add of_clk_hw_register() API for early clk
drivers") introduces a new API for registering clks, which allows the
user to directly specify a device node, even if there is no struct
device attached to it. The device node is used for local DT clock-names
matching.
Switch to of_clk_hw_register() so that local DT clock-names matching
works.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:58:20 +0000 (11:58 +0800)]
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers to specify parents using a combination of
device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add a new macro, CLK_FIXED_FACTOR_FW_NAME, that takes a string to match
a clock-names entry in the device tree to specify the clock parent.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 6 May 2019 02:43:16 +0000 (10:43 +0800)]
clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw *
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HWS, that can take an array of pointers
to struct clk_hw, instead of a string, as its parent. Taking an array
instead of a direct pointer allows the reuse of the array for multiple
clks, rather than having one compound literal with the same contents
allocated for each clk declaration.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Sun, 21 Apr 2019 23:19:46 +0000 (07:19 +0800)]
clk: fixed-factor: Add CLK_FIXED_FACTOR_HW which takes clk_hw pointer as parent
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HW, that can take a struct clk_hw
pointer, instead of a string, as its parent.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Sun, 21 Apr 2019 23:17:50 +0000 (07:17 +0800)]
clk: Add CLK_HW_INIT_PARENT_DATA macro using .parent_data
With the new clk parenting code, struct clk_init_data was expanded to
include .parent_data, for clk drivers that have parents referenced using
a combination of device tree clock-names, clock indices, and/or struct
clk_hw pointers.
Add a new macro that can take a list of struct clk_parent_data for
drivers to use.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:49:03 +0000 (11:49 +0800)]
clk: Add CLK_HW_INIT_FW_NAME macro using .fw_name in .parent_data
With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers that have parents referenced using a
combination of device tree clock-names, clock indices, and/or clk_hw
pointers.
Add a CLK_HW_INIT macro for specifying a single parent from the device
tree using .fw_name in struct clk_parent_data.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Sun, 21 Apr 2019 23:15:05 +0000 (07:15 +0800)]
clk: Add CLK_HW_INIT_* macros using .parent_hws
With the new clk parenting code, struct clk_init_data was expanded to
include .parent_hws, for clk drivers to directly list parents by
pointing to their respective struct clk_hw's.
Add macros that can take either one single struct clk_hw *, or an array
of them, for drivers to use.
A special CLK_HW_INIT_HWS macro is included, which takes an array of
struct clk_hw *, but sets .num_parents to 1. This variant is to allow
the reuse of the array, instead of having a compound literal allocated
for each clk sharing the same parent.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Fri, 3 May 2019 03:15:09 +0000 (11:15 +0800)]
clk: Fix debugfs clk_possible_parents for clks without parent string names
Following the commit
fc0c209c147f ("clk: Allow parents to be specified
without string names"), the parent name string is not always populated.
Instead, fetch the parents clk_core struct using the appropriate helper,
and read its name directly. If that fails, go through the possible
sources of parent names. The order in which they are used is different
from how parents are looked up, with the global name having precedence
over local fw_name and indices. This makes more sense as a) the
parent_maps structure does not differentiate between legacy global names
and fallback global names, and b) global names likely provide more
information than local fw_names.
Fixes:
fc0c209c147f ("clk: Allow parents to be specified without string names")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Fabrizio Castro [Tue, 11 Jun 2019 13:06:39 +0000 (14:06 +0100)]
clk: renesas: r8a774a1: Add TMU clock
This patch adds the TMU clocks to the R8A774A1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 6 Jun 2019 14:22:08 +0000 (16:22 +0200)]
clk: renesas: r8a77995: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car D3.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 6 Jun 2019 14:22:07 +0000 (16:22 +0200)]
clk: renesas: r8a77990: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car E3.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 6 Jun 2019 14:22:06 +0000 (16:22 +0200)]
clk: renesas: r8a77965: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car M3-N.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 6 Jun 2019 14:22:05 +0000 (16:22 +0200)]
clk: renesas: r8a7795: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car H3.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Anson Huang [Mon, 10 Jun 2019 05:39:22 +0000 (13:39 +0800)]
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
i.MX8MQ clock driver uses platform driver model, better to use
devm_platform_ioremap_resource() instead of of_iomap() to get
IO base.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Anson Huang [Mon, 10 Jun 2019 05:36:34 +0000 (13:36 +0800)]
clk: imx8mq: Use imx_check_clocks() API directly
Use imx_check_clocks() API to check clocks directly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Anson Huang [Mon, 10 Jun 2019 05:36:33 +0000 (13:36 +0800)]
clk: imx: Remove __init for imx_check_clocks() API
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_check_clocks() API, so
imx_check_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marc Gonzalez [Wed, 12 Jun 2019 15:03:56 +0000 (17:03 +0200)]
clk: xgene: Don't build COMMON_CLK_XGENE by default
Building COMMON_CLK_XGENE is pointless, unless we're building for
an XGENE system.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tero Kristo [Tue, 28 May 2019 13:10:24 +0000 (16:10 +0300)]
firmware: ti_sci: extend clock identifiers from u8 to u32
Future SoCs are going to have more than 255 device clocks in certain cases,
and thus the API must be extended to support this. The support is done in
backwards compatible extension, in which the new u32 clock identifier
fields are only used if the existing u8 size clock identifier is set as
255. In all the other cases, the existing u8 clock identifier is used. As
the size of the messages sent / received is not verified for existing
devices / old firmware, increasing the size of the messages from the end
is also fine. Due to this reason, depending on ABI version isn't necessary
either.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>