Shawn Guo [Tue, 22 Feb 2022 07:00:09 +0000 (15:00 +0800)]
Merge branch 'imx/defconfig' into for-next
Shawn Guo [Tue, 22 Feb 2022 07:00:08 +0000 (15:00 +0800)]
Merge branch 'imx/dt64' into for-next
Shawn Guo [Tue, 22 Feb 2022 07:00:07 +0000 (15:00 +0800)]
Merge branch 'imx/dt' into for-next
Shawn Guo [Tue, 22 Feb 2022 07:00:06 +0000 (15:00 +0800)]
Merge branch 'imx/bindings' into for-next
Shawn Guo [Tue, 22 Feb 2022 07:00:05 +0000 (15:00 +0800)]
Merge branch 'imx/soc' into for-next
Richard Zhu [Mon, 21 Feb 2022 06:33:56 +0000 (14:33 +0800)]
ARM: dts: imx6qp-sabresd: Enable PCIe support
In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
is powered up by vgen3 and used as the PCIe reference clock source by
the endpoint device.
If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
has to be in bypass mode, and ENET clocks would be messed up.
To keep things simple, let RC use the internal PLL as reference clock
and set vgen3 always on to enable the external oscillator for endpoint
device on i.MX6QP sabresd board.
NOTE: This reference clock setup is used to pass the GEN2 TX compliance
tests, and isn't recommended as a setup in the end-user design.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Ivan Bornyakov [Tue, 22 Feb 2022 05:20:59 +0000 (08:20 +0300)]
bus: imx-weim: add DT overlay support for WEIM bus
Add OF reconfiguration notifier handler for WEIM bus to setup Chip
Select timings on runtime creation of child devices.
However, it is not possible to load another DT overlay with conflicting
CS timings with previously loaded overlay, even if the first one is
unloaded. The reason is that there is no acces to CS timing property of
a device node being removed, thus we can't track which of configured CS
are available for re-configuration.
Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Jonas Kuenstler [Fri, 18 Feb 2022 12:04:58 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.
Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:57 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4
LDO4 is not connected so disable it. And LDO5 is used for VSEL of
the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an
impact on the functionality. We enable it, as it is used.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:56 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
Add bindings for VDD_ARM (BUCK2) run and standby voltage.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:55 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Update WDOG muxing
To be able to trigger a reset also from an external source we
need to configure the WDOG pin as open drain.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:54 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
Reduce drive strength on fec tx lines for signal quality improvements.
Measurements showed that TD0 and TD1 require X4 and the other lines
X2 for optimized settings.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:53 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Teresa Remmet [Fri, 18 Feb 2022 12:04:52 +0000 (13:04 +0100)]
arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy
To fit spec requirements set minimum output impedance for dp83867
ethernet phy.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 14 Feb 2022 23:14:24 +0000 (15:14 -0800)]
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- has its own on-board 24MHz osc so no clock required from baseboard
- pin 11 enables 1.8V and 2.8V LDO which is connected to
GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio
Support is added via a device-tree overlay.
The IMX219 supports RAW8/RAW10 image formats.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 14 Feb 2022 23:14:23 +0000 (15:14 -0800)]
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- has its own on-board 24MHz osc so no clock required from baseboard
- pin 11 enables 1.8V and 2.8V LDO which is connected to
GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio
controlled regulator enable.
Support is added via a device-tree overlay.
The IMX219 supports RAW8/RAW10 image formats.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 14 Feb 2022 23:14:22 +0000 (15:14 -0800)]
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes
The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol
RS-232/RS-485/RS-422 transceiver to an off-board connector which
can be configured in a number of ways via UART and GPIO configuration.
The default configuration per the imx8mm-venice-gw72xx-0x dts is for
UART2 TX/RX and UART4 TX/RX to be available as RS-232:
J15.1 UART2 TX out
J15.2 UART2 RX in
J15.3 UART4 TX out
J15.4 UART4 RX in
J15.5 GND
Add dt overlays to allow additional the modes of operation:
rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control)
J15.1 TX out
J15.2 RX in
J15.3 RTS out
J15.4 CTS in
J15.5 GND
rs485 (UART2 RS-485 half duplex)
J15.1 TXRX-
J15.2 N/C
J15.3 TXRX+
J15.4 N/C
J15.5 GND
rs422 (UART2 RS-422 full duplex)
J15.1 TX-
J15.2 RX+
J15.3 TX+
J15.4 RX-
J15.5 GND
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 14 Feb 2022 23:14:21 +0000 (15:14 -0800)]
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes
The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol
RS-232/RS-485/RS-422 transceiver to an off-board connector which
can be configured in a number of ways via UART and GPIO configuration.
The default configuration per the imx8mm-venice-gw73xx-0x dts is for
UART2 TX/RX and UART4 TX/RX to be available as RS-232:
J15.1 UART2 TX out
J15.2 UART2 RX in
J15.3 UART4 TX out
J15.4 UART4 RX in
J15.5 GND
Add dt overlays to allow additional the modes of operation:
rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control)
J15.1 TX out
J15.2 RX in
J15.3 RTS out
J15.4 CTS in
J15.5 GND
rs485 (UART2 RS-485 half duplex)
J15.1 TXRX-
J15.2 N/C
J15.3 TXRX+
J15.4 N/C
J15.5 GND
rs422 (UART2 RS-422 full duplex)
J15.1 TX-
J15.2 RX+
J15.3 TX+
J15.4 RX-
J15.5 GND
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Fri, 11 Feb 2022 19:04:17 +0000 (11:04 -0800)]
dt-bindings: arm: imx: add imx8mm gw7903 support
The GW7903 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- software selectable RS232/RS485/RS422 serial transceiver
- PMIC
- 2x off-board bi-directional opto-isolated digital I/O
- 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe
(resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Fri, 11 Feb 2022 19:04:18 +0000 (11:04 -0800)]
arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support
The GW7903 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- software selectable RS232/RS485/RS422 serial transceiver
- PMIC
- 2x off-board bi-directional opto-isolated digital I/O
- 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe
(resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Michael Walle [Mon, 14 Feb 2022 11:55:29 +0000 (12:55 +0100)]
arm64: dts: ls1028a: add efuse node
Layerscape SoCs contain a Security Fuse Processor which is basically a
efuse controller. Add the node, so userspace can read the efuses.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Hugo Villeneuve [Fri, 11 Feb 2022 15:38:43 +0000 (10:38 -0500)]
arm64: dts: imx8mp-evk: add support for I2C5
Add support for i2c5, which is used to access the
external I2C bus on connector J22 of the imx8mp-evk.
Limit the speed to 100kHz since this is an external I2C bus.
Disabled by default, since it is shared with the CAN1 bus.
To enable i2c5, you need to disable the CAN1 function, enable the i2c5
function and also configure the CAN1/I2C5_SEL GPIO to HIGH to
select i2c5 instead of CAN1. This can be done by defining a gpio-hog
inside the pca6416 node, in your board device tree, like in this example:
&flexcan1 {
status = "disabled";
};
&i2c5 {
status = "okay";
};
&pca6416 {
can1-i2c5-sel-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "can1-i2c5-sel";
};
};
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Hugo Villeneuve [Fri, 11 Feb 2022 15:38:17 +0000 (10:38 -0500)]
arm64: dts: imx8mp-evk: add PCA6416 gpio line names
Add gpio-line-names for the various GPIO's connected to the PCA6416
I/O expander on the imx8mp EVK.
This helps when using the new gpiod interface to find the GPIOs by name.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oliver Graute [Wed, 9 Feb 2022 15:50:55 +0000 (16:50 +0100)]
arm64: dts: imx8qm: added more serial alias to dts
Add more serial alias to imx8qm.dtsi file
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oliver Graute [Wed, 9 Feb 2022 15:42:23 +0000 (16:42 +0100)]
arm64: dts: imx8qm: add compatible string for usdhc3
add compatible string for usdhc3
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Ming Qian [Wed, 26 Jan 2022 03:09:31 +0000 (11:09 +0800)]
firmware: imx: scu-pd: imx8q: add vpu mu resources
the vpu core depends on the mu resources.
if they're missed, the vpu can't work.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oleksij Rempel [Fri, 11 Feb 2022 13:30:35 +0000 (14:30 +0100)]
ARM: dts: imx6dl: plym2m, prtvt7, victgo: add thermal zones and hwmon
Add thermal zones and hwmon connected to the ADC-touchscreen controller.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oleksij Rempel [Fri, 11 Feb 2022 13:30:34 +0000 (14:30 +0100)]
ARM: dts: imx6dl: plym2m, prtvt7, victgo: make use of new resistive-adc-touch driver
The tsc2046 is an ADC used as touchscreen controller. To share as mach
code as possible, we should use it as actual ADC + virtual touchscreen
controller.
With this patch we make use of the new kernel IIO and HID infrastructure.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oleksij Rempel [Fri, 11 Feb 2022 13:30:33 +0000 (14:30 +0100)]
ARM: dts: imx6qdl-vicut1: add CAN termination support
The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So,
remove wrong regulator and assign this gpio to new DT CAN termination
property.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Robin van der Gracht [Fri, 11 Feb 2022 13:30:32 +0000 (14:30 +0100)]
ARM: dts: imx6dl-prtvt7: Add missing tvp5150 video decoder node
Add missing tvp5150 video decoder node to make composite video input
work.
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Oleksij Rempel [Fri, 11 Feb 2022 13:30:31 +0000 (14:30 +0100)]
ARM: dts: imx6dl-prtvt7: Add display and panel nodes
Add Innolux G070Y2-T02 panel to the Protonic VT7 board.
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 9 Feb 2022 02:06:48 +0000 (10:06 +0800)]
arm64: dts: imx8mq-evk: Add second PCIe port support
Enable the second PCIe port support on i.MX8MQ EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 8 Feb 2022 12:32:48 +0000 (13:32 +0100)]
ARM: dts: imx6qdl-mba6: Move pinmux to regulator node
GPIO2_IO00 is used by reg_pcie, move the pinmuxing to this node as well.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 8 Feb 2022 12:32:47 +0000 (13:32 +0100)]
ARM: dts: imx6qdl: tqma6: Remove obsolete comment
This comment is not valid anymore.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 8 Feb 2022 12:32:46 +0000 (13:32 +0100)]
ARM: dts: imx6qdl: tqma6: Mark gpio-buttons as wakeup-source
They are connected directly to CPU, so they can be used as wakeup source.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 8 Feb 2022 12:32:45 +0000 (13:32 +0100)]
ARM: dts: imx6qdl: tqma6: Add i2c bus recovery
Add the pinmuxing and GPIO settings for SCL/SDA for i2c1 & i2c3.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 8 Feb 2022 12:32:44 +0000 (13:32 +0100)]
ARM: dts: imx6qdl-mba6: Move rtc alias to common location
The rtc alias is identical for both mba6a and mba6b.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Mon, 7 Feb 2022 19:25:43 +0000 (20:25 +0100)]
dt-bindings: soc: add binding for i.MX8MP HSIO blk-ctrl
This adds the binding for the HSIO blk-ctrl on the i.MX8MP SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Mon, 7 Feb 2022 19:25:42 +0000 (20:25 +0100)]
dt-bindings: power: imx8mp: add defines for HSIO blk-ctrl domains
This adds the defines for the power domains provided by the HSIO
blk-ctrl on the i.MX8MP.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Mon, 7 Feb 2022 19:25:40 +0000 (20:25 +0100)]
dt-bindings: power: add defines for i.MX8MP power domain
This adds the DT defines for the GPC power domains found on the
i.MX8MP SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Mon, 7 Feb 2022 15:25:08 +0000 (16:25 +0100)]
ARM: dts: imx7: Move PCIe out of AIPS3
The AIPS3 on iMX7 is at 0x30800000 and is 0x400000 long, the PCIe IP
is not part of this AIPS range. Move it to /soc node.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-imx@nxp.com
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Mon, 7 Feb 2022 02:05:40 +0000 (10:05 +0800)]
firmware: imx: add get resource owner api
Add resource owner management API, this API could be used to check
whether M4 is under control of Linux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Sun, 6 Feb 2022 22:11:23 +0000 (23:11 +0100)]
ARM: dts: imx: Add missing LVDS decoder on M53Menlo
The M53Menlo display unit uses an LVDS-to-DPI bridge, TI DS90CF364A.
Describe this bridge in DT, otherwise the DT incorrectly describes
DPI panel attached directly to LVDS source.
Fixes:
716be61d1869 ("ARM: dts: imx53: Add Menlosystems M53 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Sat, 5 Feb 2022 17:31:01 +0000 (11:31 -0600)]
arm64: dts: imx8mm-beacon: Enable PCIe
The baseboard supports a PCIe slot with a 100MHz reference clock,
but it's controlled by a different GPIO, so a gated clock is
required.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 11 Feb 2022 09:23:22 +0000 (10:23 +0100)]
arm64: dts: freescale: add initial support for verdin imx8m mini
This patch adds the device tree to support Toradex Verdin iMX8M Mini a
computer on module which can be used on different carrier boards.
The module consists of an NXP i.MX 8M Mini family SoC (either i.MX 8M
Mini Quad or 8M Mini DualLite), a PCA9450A PMIC, a Gigabit Ethernet PHY,
1 or 2 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an
RX8130 RTC, an optional SPI CAN controller plus an optional Bluetooth/
Wi-Fi module.
Anything that is not self-contained on the module is disabled by
default.
The device tree for the Dahlia includes the module's device tree and
enables the supported peripherals of the carrier board.
The device tree for the Verdin Development Board includes the module's
device tree as well as the Dahlia one as it is a superset and supports
almost all peripherals available.
So far there is no display functionality supported at all but basic
console UART, PCIe, USB host, eMMC and Ethernet and PCIe functionality
work fine.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 11 Feb 2022 09:23:21 +0000 (10:23 +0100)]
dt-bindings: arm: fsl: add toradex,verdin-imx8mm et al.
Add toradex,verdin-imx8mm for our new Verdin iMX8M Mini modules, its
nonwifi and wifi variants and the carrier boards (both Dahlia and the
Verdin Development Board) they may be mated in.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Hugo Villeneuve [Sat, 29 Jan 2022 20:26:17 +0000 (15:26 -0500)]
arm64: dts: imx8mp-evk: add PCA6416 interrupt controller mode
Add interrupt controller mode for the pca6416 on i.MX8MP EVK board's.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shawn Guo [Wed, 26 Jan 2022 08:54:20 +0000 (16:54 +0800)]
arm64: dts: freescale: Use overlay target for simplicity
With commit
15d16d6dadf6 ("kbuild: Add generic rule to apply
fdtoverlay"), overlay target can be used to simplify the build of DTB
overlays. It also performs a cross check to ensure base DT and overlay
actually match.
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Shawn Guo [Wed, 26 Jan 2022 08:49:40 +0000 (16:49 +0800)]
arm64: dts: fsl-ls1028a-qds: Drop overlay syntax hard coding
As suggested by commit
9ae8578b517a ("of: Documentation: change overlay
example to use current syntax"), there is no need to have overlay syntax
be hard coded in the device tree source file any more.
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:49 +0000 (17:00 +0100)]
arm64: dts: imx8mm: fix strange hex notation
Fix strange hex notation with mixed lower-case and upper-case letters.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:58 +0000 (17:00 +0100)]
arm64: defconfig: enable verdin-imx8mm relevant drivers as modules
Enable various drivers which support peripherals as found on the
Verdin iMX8M Mini et al. computer/system on modules:
- CONFIG_CAN_MCP251XFD
At least one Microchip MCP2518FDT SPI CAN controller which this driver
also supports may be found on the Verdin iMX8M Mini computer/system on
module.
- CONFIG_BT_HCIUART_MRVL, CONFIG_BT_MRVL, CONFIG_BT_MRVL_SDIO and
CONFIG_MWIFIEX_SDIO
The AzureWave AW-CM276NF which these Bluetooth and Wi-Fi drivers also
support may be found on the Verdin iMX8M Mini (as well as the Apalis
iMX8, Colibri iMX8X and Verdin iMX8M Plus for that matter) computer/
system on module.
- CONFIG_SENSORS_LM75
The TI TMP75C temperature sensor which this driver also supports may be
found on the Verdin iMX8M Mini (as well as the Verdin iMX8M Plus for
that matter) computer/system on module.
- CONFIG_SND_SOC_NAU8822
The Nuvoton Technology Corporation (NTC) NAU88C22YG which this driver
also supports may be found on the Verdin Development Board a carrier
board for the Verdin family of computer/system on module which the
Verdin iMX8M Mini (as well as the Verdin iMX8M Plus for that matter)
may be mated in.
- CONFIG_TI_ADS1015
The TLA2024 ADC which this driver also supports may be found on the
Verdin iMX8M Mini (as well as the Verdin iMX8M Plus for that matter)
computer/system on module.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:57 +0000 (17:00 +0100)]
arm64: defconfig: build r8169 as a module
Build Realtek Gigabit Ethernet driver as a module.
Network cards based on chipsets this driver supports are ubiquitous both
in regular PCIe as well as mini-PCIe and nowadays even various M.2
formats. It is therefore a suitable card to be used for any kind of PCIe
and/or Gigabit Ethernet testing. As it is not designed in, just enabling
it as a module seems most suitable.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:56 +0000 (17:00 +0100)]
arm64: defconfig: build imx-sdma as a module
This avoids firmware load error and sysfs fallback reported as follows:
[ 0.199448] imx-sdma
302c0000.dma-controller: Direct firmware load
for imx/sdma/sdma-imx7d.bin failed with error -2
[ 0.199487] imx-sdma
302c0000.dma-controller: Falling back to sysfs
fallback for: imx/sdma/sdma-imx7d.bin
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:55 +0000 (17:00 +0100)]
arm64: defconfig: enable imx8m pcie phy driver
This enables the i.MX 8M PCIe PHY driver (CONFIG_PHY_FSL_IMX8M_PCIE)
required for PCIe functionality.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:54 +0000 (17:00 +0100)]
arm64: defconfig: enable bpf/cgroup firewalling
This avoids the following systemd warning:
[ 2.618538] systemd[1]: system-getty.slice: unit configures an IP
firewall, but the local system does not support BPF/cgroup firewalling.
[ 2.630916] systemd[1]: (This warning is only shown for the first
unit using IP firewalling.)
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Song Liu <songliubraving@fb.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:53 +0000 (17:00 +0100)]
arm64: defconfig: rebuild default configuration
Run "make defconfig; make savedefconfig" to rebuild defconfig.
This dropped the following configuration options which are nowaday's
already enabled (resp. disabled) by default:
CONFIG_MEMCG_SWAP=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_FSL_MC_BUS=y
CONFIG_QCOM_SCM=y
CONFIG_MFD_CROS_EC_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_SND_SOC_FSL_SAI=m
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_XHCI_PCI=m
CONFIG_SDM_GCC_845=y
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_GCC_8150=y
CONFIG_SM_GCC_8250=y
CONFIG_COMMON_CLK_ZYNQMP=y
CONFIG_POWER_AVS was renamed to POWER_AVS_OMAP in commit
bca815d62054
("PM: AVS: smartreflex Move driver to soc specific drivers"). As there
are no 64-bit Arm OMAPs it getting dropped seems fair.
Note that the following user-selectable configuration options have been
preserved:
CONFIG_SECCOMP=y
CONFIG_SLIMBUS=m
CONFIG_INTERCONNECT=y
CONFIG_CONFIGFS_FS=y
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:52 +0000 (17:00 +0100)]
arm64: defconfig: re-order default configuration
Use "make defconfig", "make savedefconfig" and friends to just assess
re-ordering of configuration items in defconfig.
This re-ordered the following configuration options:
CONFIG_BPF_JIT=y
CONFIG_SECCOMP=y
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_INTEL_STRATIX10_SERVICE=y
CONFIG_INTEL_STRATIX10_RSU=m
CONFIG_QCOM_SCM=y
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_IMX_SCU=y
CONFIG_IMX_SCU_PD=y
CONFIG_CAN_FLEXCAN=m
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_FSL_MC_BUS=y
CONFIG_MTK_DEVAPC=m
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MESON_GXL_PHY=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_QCOM_CPR=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_MFD_CROS_EC_DEV=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
CONFIG_SND_SOC_FSL_SAI=m
CONFIG_SND_SOC_IMX_AUDMIX=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_ZYNQMP=y
CONFIG_IPQ_GCC_8074=y
CONFIG_SM_DISPCC_8250=y
CONFIG_QCOM_WCNSS_CTRL=m
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A77995=y
CONFIG_ARCH_R8A77990=y
CONFIG_ARCH_R8A77965=y
CONFIG_ARCH_R8A77970=y
CONFIG_ARCH_R8A779F0=y
CONFIG_HISI_PMU=y
CONFIG_QCOM_QFPROM=y
CONFIG_MUX_MMIO=y
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:51 +0000 (17:00 +0100)]
arm64: defconfig: enable pcieaer configuration
Enable CONFIG_PCIEAER which is required for CONFIG_ACPI_APEI_PCIEAER.
Commit
8c8ff55b4da7 ("PCI/AER: Don't select CONFIG_PCIEAER by default")
changed it to no longer being enabled by default.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Fri, 28 Jan 2022 16:00:50 +0000 (17:00 +0100)]
arm64: defconfig: enable taskstats configuration
Enable CONFIG_TASKSTATS which is required for CONFIG_TASK_XACCT (and
subsequently CONFIG_TASK_IO_ACCOUNTING). Previously, taskstats got
pulled in by KVM but that got changed in commit
63b3f96e1a98
("kvm: Select SCHED_INFO instead of TASK_DELAY_ACCT").
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Yunus Bas [Fri, 28 Jan 2022 07:27:38 +0000 (08:27 +0100)]
ARM: dts: imx6qdl-phytec: handle unneeded MFD-subdevices correctly
The proper way to handle partly used MFD devices are to describe all MFD
subdevices in the devicetree and disable the not used ones. This
suppresses any warnings that may arise as a result.
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Andrej Picej [Fri, 28 Jan 2022 07:27:37 +0000 (08:27 +0100)]
ARM: dts: imx6qdl-phytec: add missing pmic MFD subdevices
phyFLEX PMIC DA9063 has also RTC and watchdog support. Add both
MFD subdevices so they can be used.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Reinhold Mueller [Thu, 27 Jan 2022 15:35:00 +0000 (16:35 +0100)]
arm64: dts: imx8mm: Add support for emtrion emCON-MX8M Mini
This patch adds support for the emtrion GmbH emCON-MX8M Mini modules.
They are available with NXP i.MX 8M Mini equipped with 2 or 4 GB Memory.
The devicetree imx8mm-emcon.dtsi is the common part providing all
module components and the basic support for the SoC. The support for the
avari baseboard in the developer-kit configuration is provided by the
emcon-avari dts files.
Signed-off-by: Reinhold Mueller <reinhold.mueller@emtrion.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Reinhold Mueller [Thu, 27 Jan 2022 15:34:59 +0000 (16:34 +0100)]
dt-bindings: arm: Add emtrion hardware emCON-MX8M Mini
This patch presents the yaml patch for the emtrion GmbH
emCON-MX8M Mini.
Signed-off-by: Reinhold Mueller <reinhold.mueller@emtrion.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Abel Vesa [Thu, 27 Jan 2022 14:10:51 +0000 (16:10 +0200)]
ARM: dts: imx7: Use audio_mclk_post_div instead audio_mclk_root_clk
The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790),
but according to the reference manual, there is no such gate. Moreover,
the consumer driver of the mentioned clock might gate it and leave
the ECSPI2 (the true owner of that gate) hanging. So lets use the
audio_mclk_post_div, which is the parent.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Wed, 26 Jan 2022 13:23:38 +0000 (14:23 +0100)]
arm64: dts: tqma8mqml: add PCIe support
Add PCIe support to TQMa8MxML series.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Tue, 25 Jan 2022 17:11:28 +0000 (11:11 -0600)]
arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
There are two decoders on the i.MX8M Mini controlled by the
vpu-blk-ctrl. The G1 supports H264 and VP8 while the
G2 support HEVC and VP9.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Tue, 25 Jan 2022 17:11:24 +0000 (11:11 -0600)]
arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
With the Hantro G1 and G2 now setup to run independently, update
the device tree to allow both to operate. This requires the
vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
certain clock enabled to handle the gating of the G1 and G2
fuses, the clock-parents and clock-rates for the various VPU's
to be moved into the pgc_vpu because they cannot get re-parented
once enabled, and the pgc_vpu is the highest in the chain.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shawn Guo [Fri, 11 Feb 2022 03:21:29 +0000 (11:21 +0800)]
Adam Ford [Tue, 25 Jan 2022 17:11:18 +0000 (11:11 -0600)]
arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
The vpu is enabled by default, so there is no need to manually
enable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Li Yang [Wed, 26 Jan 2022 09:26:50 +0000 (03:26 -0600)]
arm64: dts: ls1028a-qds: define mdio slots for networking options
The ls1028a QDS board support different pluggable PHY cards. Define the
nodes for these slots to be updated at boot time with overlay according
to board setup.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Fri, 28 Jan 2022 01:06:03 +0000 (17:06 -0800)]
arm64: dts: imx8m{m,n}_venice*: add gpio-line-names
Add gpio-line-names for the various GPIO's used on Gateworks Venice
boards. Note that these GPIO's are typically 'configured' in Boot
Firmware via gpio-hog therefore we only configure line names to keep the
boot firmware configuration from changing on kernel init.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Thu, 16 Dec 2021 16:12:27 +0000 (08:12 -0800)]
arm64: dts: imx8mn-venice-gw7902: disable gpu
Since commit
9a0f3b157e22 ("arm64: dts: imx8mn: Enable GPU")
imx8mn-venice-gw7902 will hang during kernel init because it uses
a MIMX8MN5CVTI which does not have a GPU.
Disable pgc_gpumix to work around this. We also disable the GPU devices
that depend on the gpumix power domain and pgc_gpu to avoid them staying
in a probe deferred state forever.
Cc: Adam Ford <aford173@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fixes:
9a0f3b157e22 ("arm64: dts: imx8mn: Enable GPU")
Reviewed-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Tue, 25 Jan 2022 02:54:09 +0000 (03:54 +0100)]
arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B
The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020
documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the
pinmux tables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Wed, 19 Jan 2022 13:23:48 +0000 (14:23 +0100)]
arm64: dts: imx8mp: disable usb3_phy1
Like usb3_phy0 the default state of the usb3_phy1 should be disabled, so
it is only enabled on boards exposing this USB port.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Abel Vesa [Tue, 18 Jan 2022 13:59:18 +0000 (15:59 +0200)]
arm64: dts: imx8qxp-ss-adma: Drop fsl,imx7ulp-lpuart comaptible
The driver differs from clocks point of view, so the i.MX8QXP
is not backwards compatible with i.MX7ULP.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 11 Jan 2022 06:20:13 +0000 (14:20 +0800)]
arm64: dts: imx8: add mu5/6 node
Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Abel Vesa [Mon, 3 Jan 2022 22:49:00 +0000 (00:49 +0200)]
arm64: dts: imx8qm: Add SCU RTC node
Add SCU RTC node to support SC RTC driver.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 18 Dec 2021 18:20:21 +0000 (19:20 +0100)]
arm64: dts: mnt-reform2: correct i2c3 pad-ctrl
The slew rate and drive-strength of the i2c3 pads were much too
high. Bring them down to avoid signal quality issues.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 18 Dec 2021 18:20:20 +0000 (19:20 +0100)]
arm64: dts: mnt-reform2: add internal display support
This adds support for the internal display of the Reform2 Laptop, which
is connected to the i.MX8MQ via a MIPI-DSI->eDP bridge chip. Clocking
is derived from a system PLL, which provides quite good rate matching
for the single supported display mode and keeps the video PLL free for
usage with the external display, which isn't supported yet.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 18 Dec 2021 18:18:08 +0000 (19:18 +0100)]
arm64: dts: imx8mq: disable DDRC node by default
Without a OPP table or a downstream TF-A running on the system the DDRC will
fail to probe, as it has no means to scale the DRAM frequency in that case.
This however will block the bus scaling driver to come up and this in turn
prevents other devices that hook into the interconnect from probing.
If the DDRC is disabled, the interconnect driver will simply ignore it. As
most systems don't want to scale the DRAM frequency, disable the node by
default and only enable it on the systems that actually uses this
capability and provides a valid OPP table in the DT.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
David Jander [Fri, 17 Dec 2021 21:36:17 +0000 (22:36 +0100)]
arm64: dts: imx: add Protonic PRT8MM board
The Protonic PRT8MM is a low-cost agricultural Virtual Terminal. This
commit adds most of the board functionality sans the display output,
as the i.MX8MM display support isn't ready yet.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rob Herring [Fri, 17 Dec 2021 17:39:08 +0000 (11:39 -0600)]
arm64: dts: imx8qm: Drop CPU 'arm,armv8' compatible
The CPU 'arm,armv8' compatible is only for s/w models, so remove it from
i.MX8QM CPU nodes.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Thu, 16 Dec 2021 16:41:49 +0000 (08:41 -0800)]
arm64: dts: imx8mm-venice*: add PCIe support
Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:26 +0000 (18:46 -0600)]
arm64: dts: imx8mn: Enable GPU
The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:
etnaviv-gpu
38000000.gpu: model: GC7000, revision: 6203
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:25 +0000 (18:46 -0600)]
arm64: dts: imx8mn: add DISP blk-ctrl
Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains should be functional.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:24 +0000 (18:46 -0600)]
arm64: dts: imx8mn: put USB controller into power-domains
Now that we have support for the power domain controller on the i.MX8MN,
we can put the USB controller in the respective power domain to allow
it to power down the PHY when possible.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adam Ford [Wed, 15 Dec 2021 00:46:23 +0000 (18:46 -0600)]
arm64: dts: imx8mn: add GPC node
Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Thu, 2 Dec 2021 08:02:37 +0000 (16:02 +0800)]
arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board
Add the PCIe support on iMX8MM EVK boards.
And set the default reference clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Thu, 2 Dec 2021 08:02:36 +0000 (16:02 +0800)]
arm64: dts: imx8mm: Add the pcie support
Add the PCIe support on i.MX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Thu, 2 Dec 2021 08:02:34 +0000 (16:02 +0800)]
arm64: dts: imx8mm: Add the pcie phy support
Add the PCIe PHY support on iMX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Tue, 25 Jan 2022 17:11:21 +0000 (11:11 -0600)]
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to
avoid putting more of this functionality into the decoder driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shawn Guo [Fri, 11 Feb 2022 02:51:23 +0000 (10:51 +0800)]
Lucas Stach [Fri, 17 Dec 2021 21:36:16 +0000 (22:36 +0100)]
dt-bindings: arm: imx: add Protonic PRT8MM board compatible
Add the compatible string for the Protonic PRT8MM board, which is a
reference design for a low-cost agricultural terminal.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Tue, 25 Jan 2022 17:11:19 +0000 (11:11 -0600)]
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
This adds the defines for the power domains provided by the VPU
blk-ctrl on the i.MX8MQ.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Tue, 25 Jan 2022 17:11:20 +0000 (11:11 -0600)]
dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
This adds the DT binding for the i.MX8MQ VPU blk-ctrl.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Dario Binacchi [Mon, 17 Jan 2022 16:17:52 +0000 (17:17 +0100)]
ARM: dts: imx28: reparent gpmi clock to ref_gpmi
Since ref_gpmi is sourced from pll0 (480MHz), It allows the GPMI
controller to manage High-Speed NAND Timing (edo mode 3,4 and 5).
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Tested-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Giulio Benetti [Tue, 11 Jan 2022 21:54:15 +0000 (16:54 -0500)]
ARM: imxrt_defconfig: Add i.MXRT family defconfig
Add generic i.MXRT family defconfig.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Jesse Taube [Tue, 11 Jan 2022 21:54:10 +0000 (16:54 -0500)]
ARM: dts: imxrt1050-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1050 pinctrl device tree.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: move pinfunc from dt-bindings to dts folder]
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Giulio Benetti [Tue, 11 Jan 2022 21:54:09 +0000 (16:54 -0500)]
ARM: imx: Add initial support for i.MXRT10xx family
The i.MXRT10xx family of processors features NXP's implementation of the
Arm Cortex-M7 core and in some case the Arm Cortex-M4 core too.
This patch aims to add an initial support for imxrt.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: removed SOC_IMXRT's 'depends on ARCH_MULTI_V7' and 'select
ARM_GIC if ARCH_MULTI_V7']
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabio Estevam [Wed, 8 Dec 2021 20:12:11 +0000 (17:12 -0300)]
soc: imx: Remove Layerscape check
Since commit
4ebd29f91629 ("soc: imx: Register SoC device only on i.MX
boards") the soc-imx driver is only registered on i.MX platforms as
intended.
This means that we no longer need to do a specific check for
Layerscape.
Remove the now unneeded "fsl,ls1021a" check.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
projects / linux-2.6-block.git / log