arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant

As most other board Miix uses board-id = 0xff, so define calibration
variant to distinguish it from other devices with the same chip_id.

qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40010002

Cc: Kalle Valo <kvalo@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240723-miix630-support-v2-5-7d98f6047a17@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown

Let resin device generate the VolumeDown key.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240723-miix630-support-v2-4-7d98f6047a17@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button

Add gpio-keys device, responsible for a single button: Volume Up.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240723-miix630-support-v2-3-7d98f6047a17@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI

Enable two other DSP instances on this platofm, aDSP and SLPI.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240723-miix630-support-v2-2-7d98f6047a17@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen

There is no point in keeping touchscreen disabled, enable corresponding
i2c-hid device.

04F3:2608 Touchscreen as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input1
04F3:2608 as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input2
04F3:2608 as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input3
04F3:2608 Stylus as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input4

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240723-miix630-support-v2-1-7d98f6047a17@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes

Enable PCIe1 controller and its corresponding PHY nodes on
qcs6490-rb3g2 platform.

SMMU v2 has limited SID's to assign dynamic SID's with the existing
logic. For now, use static iommu-map table assigning unique SID's for
each port as dynamic approach needs boarder community discussions.

PCIe switch connected to this board has 3 downstream ports and
to the one of the downstream an embedded ethernet is connected.
Assign unique SID for each downstream port and to embedded ethernet,
and also reserve a SID for the endpoints which are going to be
connected to the other two downstream ports.

As this PCIe switch is present in this platform only update iommu-map
in this platform only as other board variants might have different
PCIe topology and might need different mapping.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/20241024-enable_pcie-v2-1-e5a6f5da74e4@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-dell-xps13-9345: fix nvme regulator boot glitch

The NVMe regulator has been left enabled by the boot firmware. Mark it
as such to avoid disabling the regulator temporarily during boot.

Based on https://lore.kernel.org/all/20241016145112.24785-1-johan+linaro@kernel.org/

Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345")
Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241016202253.9677-3-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-dell-xps13-9345: route edp-panel enable gpio

tlmm 74 was experimentally found to be panel enable pin, which shall be
high for panel (both low-res IPS, OLED) to work. Define it as such.

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Link: https://lore.kernel.org/r/20241016202253.9677-2-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes

Devicetree binding has documented the node name for UFS controllers as
'ufshc'. So let's use it instead of 'ufs' which is for the UFS devices.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20240514-ufs-nodename-fix-v1-2-4c55483ac401@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcm6490-idp: Add UFS nodes

Add UFS host controller and Phy nodes for Qualcomm qcm6490-idp board.

Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Link: https://lore.kernel.org/r/20241019063659.6324-1-quic_mapa@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-17-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-16-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-15-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-14-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8550: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-13-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-12-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-11-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8250: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-10-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8150: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-9-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm6350: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-8-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm6115: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-7-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-6-0505bc7d2c56@linaro.org
[bjorn: Update sm7325 references to match the updated case]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc8280xp: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-5-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc7180: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-4-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm8992-libra: drop unused regulators labels

DTS coding style expects labels to be lowercase, but the labels are not
used, so just drop them.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-3-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: msm: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-2-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: ipq: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node

Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPUs. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...

Hence, add it to the PCIe RC node along with the existing MSI interrupts.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240828-pci-qcom-hotplug-v4-12-263a385fbbcb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes

'linux,pci-domain' property provides the PCI domain number for the PCI
endpoint controllers in a SoC. If this property is not present, then an
unstable (across boots) unique number will be assigned.

Use this property to specify the domain number based on the actual hardware
instance of the PCI endpoint controllers in SA8775P SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240828-pci-qcom-hotplug-v4-9-263a385fbbcb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: Add TCSR halt register space

Enable download mode for sa8775p which can help collect
ramdump for this SoC.

Reviewed-by: Elliot Berman <quic_eberman@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20240830133908.2246139-2-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p-ride: add WiFi/BT nodes

Add a node for the PMU module of the WCN6855 present on the sa8775p-ride
board. Assign its LDO power outputs to the existing WiFi/Bluetooth module.

Signed-off-by: Miaoqing Pan <quic_miaoqing@quicinc.com>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241011041939.2916179-1-quic_miaoqing@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: add QCrypto nodes

Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Link: https://lore.kernel.org/r/20241017144500.3968797-3-quic_yrangana@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into arm64-for-6.13

Merge SA8775P multimedia clock bindings into the DeviceTree branch to
gain access to the clock constants.

dt-bindings: clock: qcom: Add SA8775P display clock controllers

Add device tree bindings for the display clock controllers
on Qualcomm SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-5-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: qcom: Add SA8775P camera clock controller

Add device tree bindings for the camera clock controller
on Qualcomm SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-3-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: qcom: Add SA8775P video clock controller

Add device tree bindings for the video clock controller on Qualcomm
SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-1-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm7325: Add device-tree for Nothing Phone 1

Add device tree for the Nothing Phone 1 (nothing,spacewar) smartphone
which is based on the SM7325 SoC.

Supported features are, as of now:
* USB & UFS
* Debug UART
* Display via SimpleFB
* Power & volume buttons
* PMIC GLink
* Remoteprocs (ADSP, CDSP, MPSS, WPSS)
* WiFi & Bluetooth
* IPA
* VPU Iris (Venus)
* NFC
* Flash/torch LED
* RTC
* Device-specific thermals
* Various plumbing like regulators, i2c, spi, cci, etc

Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Co-developed-by: Danila Tikhonov <danila@jiaxyga.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20241020205615.211256-7-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: arm: qcom: Add SM7325 Nothing Phone 1

Nothing Phone 1 (nothing,spacewar) is a smartphone based on the SM7325
SoC.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-6-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: vendor-prefixes: Add Nothing Technology Limited

Add entry for Nothing Technology Limited (https://nothing.tech/)

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-5-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Add SM7325 device tree

The Snapdragon 778G (SM7325) / 778G+ (SM7325-AE) / 782G (SM7325-AF)
is software-wise very similar to the Snapdragon 7c+ Gen 3 (SC7280).

It uses the Kryo670.

Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-4-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: arm: cpus: Add qcom kryo670 compatible

The Qualcomm Snapdragon 778G/778G+/780G/782G uses CPUs named Kryo 670.
Add the compatible string in the documentation.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-3-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: Add GPI configuration

I2C and SPI geni driver also supports the GSI node based
on client requirements. Currently, in the DTSI, the GSI mode
configuration is not added.

Therefore, add GPI DT nodes for QUPV_0/1/2/3 for I2C and SPI
for the SA8775.

Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241021102815.12079-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region

Resize the GICR register region as it currently seeps into the CPU Control
Processor mailbox RX region.

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: rename vph-pwr regulator nodes

Rename the x1e80100 vph-pwr regulator nodes to use "regulator" as a
prefix for consistency with the other fixed regulators.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241015122601.16127-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: extend the register range for UFS ICE

The full register range for ICE on sa8775p is 0x18000 so update the
crypto node.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-3-05ee041f2fc1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8550: extend the register range for UFS ICE

The full register range for ICE on sm8550 is 0x18000 so update the
crypto node.

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-2-05ee041f2fc1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650: extend the register range for UFS ICE

The full register range for ICE on sm8650 is 0x18000 so update the
crypto node.

Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-1-05ee041f2fc1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sa8775p: Populate additional UART DT nodes

Currently, UART configuration is populated for only a few SEs
(Serial Engines) in the sa8775p DTSI file. Since every SE can
support the UART protocol, usecase or client should have the flexibility
to enable required SE for UART depending on the specific board version.

Hence, populate UART configurations for the remaining SEs in the
sa8775p SoC.

Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241007091407.13798-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-t14s: add another trackpad support

Trackpad HID device on T14s could be found on two possible slave addresses
(hid@15 and hid@2c) on i2c0 instance.
With the current state of DT boot, there is no way to patch the device
tree at runtime during boot. This, however results in non-functional
trackpad on Product Models 21N2ZC5PUS which have trackpad on hid@2c
slave address.

This patch adds hid@2c device along with hid@15 to get it working on
both the variants. This should work as i2c-hid driver will stop
probing the device if there is nothing on the slave address, we can
actually keep both devices enabled in DT, and i2c-hid driver will
only probe the existing one.

The only problem is that we cannot setup pinctrl in both device nodes,
as two devices with the same pinctrl will cause pin conflict that makes
the second device fail to probe.  Let's move the pinctrl state up to
parent node along with the parent pinctrl to solve this problem.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241004130849.2944-1-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345

Initial support for Dell XPS 9345 13" 2024 (Codenamed 'Tributo') based
on X1E80100.

Working:
* Touchpad
* Keyboard (only post suspend&resume, i2c-hid patch required [1])
* Touchscreen
* eDP (low-res IPS, OLED) with brightness control
* NVME
* USB Type-C ports in USB2/USB3 (one orientation)
* WiFi
* GPU/aDSP/cDSP firmware loading (requires binaries from Windows)
* Lid switch
* Sleep/suspend, nothing visibly broken on resume

Not working:
* Speakers (WIP, pin guessing, x4 WSA8845)
* Microphones (WIP, pin guessing, dual array)
* Fingerprint Reader (WIP, USB MP with ptn3222)
* USB as DP/USB3 (WIP, PS8830 based)
* Camera (Likely OV01A10)
* EC over i2c

Should be working, but cannot be tested due to lack of hw:
* higher res IPS panel

[1] https://lore.kernel.org/all/20240925100303.9112-1-alex.vinarskis@gmail.com/

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Link: https://lore.kernel.org/r/20241003211139.9296-4-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: arm: qcom: Add Dell XPS 13 9345

Document the X1E80100-based Dell XPS 13 9345 laptop, platform
codenamed 'Tributo'/'Tributo R'.

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Link: https://lore.kernel.org/r/20241003211139.9296-2-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c ports

The 2 USB-C ports on x1e78100-t14s are OTG-capable, remove the dr_mode
override to enable OTG.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241011231624.30628-3-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-crd: enable otg on usb ports

The 3 USB ports on x1e80100-crd are OTG-capable, remove the dr_mode
override to enable OTG.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241011231624.30628-2-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: enable OTG on USB-C controllers

These 3 controllers support OTG and the driver requires the usb-role-switch
property to enable OTG. Add the property to enable OTG by default.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241011231624.30628-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB SS[0-1] QMP PHYs

The orientation-switch is already set in the x1e80100 SoC dtsi,
so drop from Vivobook S15 dts.

Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241014-x1e80100-dts-drop-orientation-switch-v1-2-26afa6d4afd9@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] QMP PHYs

The orientation-switch is already set in the x1e80100 SoC dtsi,
so drop from Slim 7X dts.

Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241014-x1e80100-dts-drop-orientation-switch-v1-1-26afa6d4afd9@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Drop undocumented domain "idle-state-name"

"idle-state-name" is not a valid property for "domain-idle-state"
binding, so drop it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241014161631.1527918-2-robh@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin

A642L (speedbin 0x81) uses index 4, so this commit sets the fourth bit
for A642L supported opps.

Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20241014194825.44406-2-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

The DWC PCIe controller can be used with its internal MSI controller or
with an external one such as the GICv3 Interrupt Translation Service
(ITS).

Add the msi-map properties needed to use the GIC ITS. This will also
make Linux switch to the ITS implementation, which allows for assigning
affinity to individual MSIs. This specifically allows NVMe and Wi-Fi
interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error
Reporting (AER) interrupts to be received on errors unlike when using
the internal MSI controller. Consequently, notifications about
(correctable) errors may now be logged for errors that previously went
unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the
internal MSI controller due to a platform (firmware) limitation.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241009161715.14994-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcs6490-rb3gen2: Enable PWR/VOL keys

RB3Gen2 has three tiny buttons located under the blue USB-A ports.
They're all connected through the various PMICs and are used for
volume and power.

Describe them.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241004-rb3gen2-pwr-vol-keys-v1-1-4b1859c7cc4f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcs6490-rb3gen2: Specify i2c1 clock frequency

Per the binding, omitting the clock frequency from a Geni I2C controller
node defaults the bus to 100Khz. But at least in Linux, a friendly info
print highlights the lack of explicitly defined frequency in the
DeviceTree.

Specify the frequency, to give it an explicit value, and to silence the
log print in Linux.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241004-i2c1-frequency-v1-1-77a359015d54@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sda660-ifc6560: enable mDSP and WiFi devices

Enable the onboard WiFi device present on the Inforce IFC6560 SBC.
Pretty much like MSM8998 this device also doesn't generate the
MSA_READY_IND indication.

For the reference:

ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40050000
ath10k_snoc 18800000.wifi: qmi fw_version 0x101d01da fw_build_timestamp 2018-07-26 21:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.1.0.1.c2-00474-QCAHLSWMTPLZ-1
ath10k_snoc 18800000.wifi: qmi not waiting for msa_ready indicator
ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000
ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0
ath10k_snoc 18800000.wifi: firmware ver  api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790
ath10k_snoc 18800000.wifi: htt-ver 3.54 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1
ath10k_snoc 18800000.wifi: invalid MAC address; choosing random

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-7-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm630: add WiFI device node

Add device node for the WiFi device being a part of the integrated
SDM660 / SDM630 platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-6-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm630: enable A2NOC and LPASS SMMU

Now as the arm-smmu-qcom driver gained workarounds for the A2NOC and
LPASS SMMU devices, enable those two devices.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-5-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges

L10A, being a fixed regulator, should have min_voltage = max_voltage,
otherwise fixed rulator fails to probe. Fix the max_voltage range to be
equal to minimum.

Fixes: 4edbcf264fe2 ("arm64: dts: qcom: sda660-ifc6560: document missing USB PHY supplies")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-4-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sda660-ifc6560: enable GPU

Enable Adreno GPU on the Inforce IFC6560 SBC. It requires the Zap shader
binary that was provided by the vendor.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-3-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCC

Now as the arm-smmu-qcom driver gained workarounds for the Adreno SMMU,
it becomes possible to safely enable GPU on the devices. Enable GPU SMMU
and GPU clock controller. GPU should be enabled for target devices that
have ZAP shader blob.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-2-e316055142f8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcm6490-fairphone-fp5: Add thermistor for UFS/RAM

Configure the ADC and thermal zone for the thermistor next to the
UFS+RAM chip which is connected to GPIO_12 of PM7250B. It is used to
measure the temperature of that area of the PCB.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20241002-fp5-ufs-therm-v1-1-1d2d8c1f08b5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins

Make sure the GPU frequencies are marked as supported for the respective
speedbins according to downstream msm-4.19 kernel:

* 850 MHz: Speedbins 0 + 180
* 800 MHz: Speedbins 0 + 180 + 169
* 650 MHz: Speedbins 0 + 180 + 169 + 138
* 565 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 430 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 355 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 253 MHz: Speedbins 0 + 180 + 169 + 138 + 120

Fixes: bd9b76750280 ("arm64: dts: qcom: sm6350: Add GPU nodes")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20241002-sm6350-gpu-speedbin-fix-v1-1-8a5d90c5097d@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G

Add an initial devicetree for the Microsoft Surface Pro 9 5G, based
on SC8280XP.

It enables the support for Wi-Fi, NVMe, the two USB Type-C ports,
Bluetooth, 5G cellular modem, audio output (via Bluetooth headsets
or USB audio), external display via DisplayPort over Type-C (only
the bottom USB Type-C port is working so far), charging, the Surface
Aggregator Module (SAM) to get keyboard and touchpad working with
Surface Type Cover accessories.

Some key features not supported yet:
- built-in display (but software fallback is working with efifb
  when blacklisting the msm module)
- built-in display touchscreen
- external display with the top USB Type-C port
- speakers and microphones
- physical volume up and down keys
- LID switch detection

This devicetree is based on the other SC8280XP ones, for the Lenovo
ThinkPad X13s and the Qualcomm CRD.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Link: https://lore.kernel.org/r/20240908223505.21011-6-jerome.debretagne@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc8280xp: Add uart18

Add the node describing uart18 for sc8280xp devices.

Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Link: https://lore.kernel.org/r/20240908223505.21011-5-jerome.debretagne@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: arm: qcom: Document Microsoft Surface Pro 9 5G

Add compatible for the SC8280XP-based Microsoft Surface Pro 9 5G,
using its Arcata codename.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Link: https://lore.kernel.org/r/20240908223505.21011-2-jerome.debretagne@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: minor whitespace cleanup

The DTS code coding style expects exactly one space around '='
character.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-4-f4c5f7b2c8c2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: drop underscore in node names

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.

Functional impact checked with comparing before/after DTBs with dtx_diff
and fdtdump.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-3-f4c5f7b2c8c2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-romulus: Set up USB Multiport controller

The USB MP controller is wired up to the USB-A port on the left side
and to the Surface Connector on the right side. Configure it.

While at it, remove a stray double \n.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-2-3ee667e6652d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100-romulus: Add lid switch

One of the best parts of having a laptop is being able to close the lid
and go on with your day. Enable this feature by defining the lid switch.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-1-3ee667e6652d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc7280: Fix PMU nodes for Cortex A55 and A78

The SC7280, SM7325, and QCM6490 platforms feature an 8-core setup
consisting of:
- 1x Kryo 670 Prime (Cortex-A78) / Kryo 670 Gold Plus (Cortex-A78)
- 3x Kryo 670 Gold (Cortex-A78)
- 4x Kryo 670 Silver (Cortex-A55)
(The CPU cores in the SC7280 are simply called Kryo, but are
nevertheless based on the same Cortex A78 and A55).

Use the correct compatibility.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240818192905.120477-1-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: Add debug uart to Lenovo Yoga Slim 7x

This commit enables the debug UART found on the motherboard under the SSD

Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Link: https://lore.kernel.org/r/20241004192436.16195-2-maccraft123mc@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: describe tcsr download mode register

Describe the TCSR download mode register to enable download mode
control.

This specifically allows the OS to disable download mode in case the
boot firmware has left it enabled to avoid entering the crash dump mode
after a hypervisor reset by default.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241002100122.18809-3-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcs6460-rb3gen2: enable venus node

Enable the venus node on Qualcomm Rb3gen2 so that the
video decoder will start working.

Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240917-venus_rb3_gen2-v1-1-8fea70733592@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-11-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-10-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-9-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-8-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-7-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-6-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-5-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-4-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-3-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-2-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-1-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: qcs6490-rb3gen2: Add SD Card node

Add SD Card node for Qualcomm qcs6490-rb3gen2 Board.

Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240919084826.1117-1-quic_sachgupt@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650-qrd: remove status property from dispcc device tree node

After a change enabling display clock controller for all Qualcomm SM8650
powered board by default there is no more need to set a status property
of dispcc on SM8650-QRD board.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-10-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650-mtp: remove status property from dispcc device tree node

After a change enabling display clock controller for all Qualcomm SM8650
powered board by default there is no more need to set a status property
of dispcc on SM8650-MTP board.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-9-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650-hdk: remove status property from dispcc device tree node

After a change enabling display clock controller for all Qualcomm SM8650
powered board by default there is no more need to set a status property
of dispcc on SM8650-HDK board.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-8-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8650: don't disable dispcc by default

Enable display clock controller for all Qualcomm SM8650 powered boards
by default.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-7-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450-hdk: remove status property from dispcc device tree node

After a change enabling display clock controller for all Qualcomm SM8450
powered board by default there is no more need to set a status property
of dispcc on SM8450-HDK board.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-6-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450: don't disable dispcc by default

Enable display clock controller for all Qualcomm SM8450 powered boards
by default.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-5-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450-sony-xperia-nagara: disable dispcc on derived boards

A platform display clock controller is expected to be enabled by default
for all boards, however in particular cases preset display clock setting
is expected. To avoid any probable regression before enabling display
clock controller for all SM8450 platforms disable it for SM8450 powered
Sony Xperia phones.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-4-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8450-qrd: explicitly disable dispcc on the board

A platform display clock controller is expected to be enabled by default
for all boards, however in particular cases preset display clock setting
is expected. To avoid any probable regression before enabling display
clock controller for all SM8450 platforms disable it for SM8450-QRD board
only.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240924100602.3813725-3-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>