From: Ramuthevar Vadivel Murugan Date: Tue, 24 Nov 2020 04:18:40 +0000 (+0800) Subject: dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi X-Git-Tag: v5.12-rc1~116^2^2~32^2 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=fcebca39938fa9f6ed03f27fc75645ad7fd489e9;p=linux-block.git dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi Add new vendor specific compatible string to check Intel's Lightning Mountain(LGM) QSPI features enablement in cadence-quadspi driver. Signed-off-by: Ramuthevar Vadivel Murugan Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201124041840.31066-6-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt index 945be7d5b236..8ace832a2d80 100644 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt @@ -5,6 +5,7 @@ Required properties: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the