From: George Moussalem Date: Mon, 30 Jun 2025 12:35:00 +0000 (+0400) Subject: clk: qcom: gcc-ipq5018: fix GE PHY reset X-Git-Tag: io_uring-6.17-20250815~88^2~2^6^2~39 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=f6a4a55ae5d99f865e106916a9295548e381de47;p=linux-block.git clk: qcom: gcc-ipq5018: fix GE PHY reset The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932 Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com Signed-off-by: Bjorn Andersson --- diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 24eb4c40da63..dcda2be8c1a5 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, [GCC_WCSSAON_RESET] = { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) }, }; static const struct of_device_id gcc_ipq5018_match_table[] = {