From: Jisheng Zhang <jszhang@marvell.com>
Date: Tue, 18 Jul 2017 06:48:21 +0000 (+0800)
Subject: PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically
X-Git-Tag: v4.14-rc1~87^2~19^2~9
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=e9be4d78618af2e0d5592d9556cf0bba210cfd1a;p=linux-2.6-block.git

PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically

The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
be set.  To check whether the ATU is enabled or not, we should test the
enable bit specifically.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
---

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index ebcdce219acb..50cef47fc25d 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -178,7 +178,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 	 */
 	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
 		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
-		if (val == PCIE_ATU_ENABLE)
+		if (val & PCIE_ATU_ENABLE)
 			return;
 
 		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);