From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed, 2 Sep 2015 12:33:42 +0000 (+0200)
Subject: Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
X-Git-Tag: v4.4-rc1~44^2~33^2~46
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=e93c28f39375558409329a02a767d5cadfcc4a31;p=linux-2.6-block.git

Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued

Backmerge -fixes since there's more DDI-E related cleanups on top of
the pile of -fixes for skl that just landed for 4.3.

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i914/intel_dp.c
	drivers/gpu/drm/i915/intel_lrc.c

Conflicts are all fairly harmless adjacent line stuff.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---

e93c28f39375558409329a02a767d5cadfcc4a31
diff --cc drivers/gpu/drm/i915/intel_dp.c
index f45872cc6d24,0a2e33fbf20d..f8f4d99440c1
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -3993,9 -3909,15 +4000,14 @@@ intel_dp_get_dpcd(struct intel_dp *inte
  		}
  	}
  
- 	/* Training Pattern 3 support, both source and sink */
+ 	/* Training Pattern 3 support, Intel platforms that support HBR2 alone
+ 	 * have support for TP3 hence that check is used along with dpcd check
+ 	 * to ensure TP3 can be enabled.
+ 	 * SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is
+ 	 * supported but still not enabled.
+ 	 */
 -	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
 -	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
 +	if (drm_dp_tps3_supported(intel_dp->dpcd) &&
- 	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+ 	    intel_dp_source_supports_hbr2(dev)) {
  		intel_dp->use_tps3 = true;
  		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
  	} else
diff --cc drivers/gpu/drm/i915/intel_lrc.c
index e9520afc2033,72e0edd7bbde..40cbba4ea4ba
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@@ -1027,9 -1004,7 +1027,11 @@@ static int intel_lr_context_pin(struct 
  		if (ret)
  			goto unpin_ctx_obj;
  
+ 		ctx_obj->dirty = true;
++
 +		/* Invalidate GuC TLB. */
 +		if (i915.enable_guc_submission)
 +			I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
  	}
  
  	return ret;