From: Hang Yuan Date: Tue, 30 Oct 2018 07:08:01 +0000 (+0800) Subject: drm/i915/gtt: Revert "Disable read-only support under GVT" X-Git-Tag: for-linus-20190104~57^2~17^2~177 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=e5ee4956f2fdda8ac2d3eab309df389d43b80fc0;p=linux-2.6-block.git drm/i915/gtt: Revert "Disable read-only support under GVT" This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd. Checked GVT codes that guest PPGTT PTE flag bits are propagated to shadow PTE. Read/write bit is not changed. Further tested by i915 self-test case "igt_ctx_readonly". No error or GPU hang was detected. So enable read-only support under GVT. Signed-off-by: Hang Yuan Acked-by: Zhenyu Wang Link: https://patchwork.freedesktop.org/patch/msgid/1540883281-11359-1-git-send-email-hang.yuan@linux.intel.com Acked-by: Chris Wilson Signed-off-by: Chris Wilson --- diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9ea024395d49..a98c29147d5e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1625,12 +1625,8 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) 1ULL << 48 : 1ULL << 32; - /* - * From bdw, there is support for read-only pages in the PPGTT. - * - * XXX GVT is not honouring the lack of RW in the PTE bits. - */ - ppgtt->vm.has_read_only = !intel_vgpu_active(i915); + /* From bdw, there is support for read-only pages in the PPGTT. */ + ppgtt->vm.has_read_only = true; i915_address_space_init(&ppgtt->vm, i915);