From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sat, 20 Jan 2024 19:06:04 +0000 (-0800)
Subject: Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Tag: v6.8-rc1~10
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=e5075d8ec5647322fb9e699bfb76331cc8ee098d;p=linux-block.git

Merge tag 'riscv-for-linus-6.8-mw4' of git://git./linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - Support for tuning for systems with fast misaligned accesses.

 - Support for SBI-based suspend.

 - Support for the new SBI debug console extension.

 - The T-Head CMOs now use PA-based flushes.

 - Support for enabling the V extension in kernel code.

 - Optimized IP checksum routines.

 - Various ftrace improvements.

 - Support for archrandom, which depends on the Zkr extension.

 - The build is no longer broken under NET=n, KUNIT=y for ports that
   don't define their own ipv6 checksum.

* tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits)
  lib: checksum: Fix build with CONFIG_NET=n
  riscv: lib: Check if output in asm goto supported
  riscv: Fix build error on rv32 + XIP
  riscv: optimize ELF relocation function in riscv
  RISC-V: Implement archrandom when Zkr is available
  riscv: Optimize hweight API with Zbb extension
  riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi
  samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI]
  riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support
  riscv: ftrace: Make function graph use ftrace directly
  riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY
  lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name
  riscv: Restrict DWARF5 when building with LLVM to known working versions
  riscv: Hoist linker relaxation disabling logic into Kconfig
  kunit: Add tests for csum_ipv6_magic and ip_fast_csum
  riscv: Add checksum library
  riscv: Add checksum header
  riscv: Add static key for misaligned accesses
  asm-generic: Improve csum_fold
  RISC-V: selftests: cbo: Ensure asm operands match constraints
  ...
---

e5075d8ec5647322fb9e699bfb76331cc8ee098d
diff --cc arch/riscv/include/asm/sbi.h
index b6f898c56940,6dd41ff3c66e..6e68f8dff76b
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@@ -29,9 -29,9 +29,10 @@@ enum sbi_ext_id 
  	SBI_EXT_RFENCE = 0x52464E43,
  	SBI_EXT_HSM = 0x48534D,
  	SBI_EXT_SRST = 0x53525354,
+ 	SBI_EXT_SUSP = 0x53555350,
  	SBI_EXT_PMU = 0x504D55,
  	SBI_EXT_DBCN = 0x4442434E,
 +	SBI_EXT_STA = 0x535441,
  
  	/* Experimentals extensions must lie within this range */
  	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
diff --cc drivers/tty/hvc/hvc_riscv_sbi.c
index a72591279f86,2f3571f17ecd..cede8a572594
--- a/drivers/tty/hvc/hvc_riscv_sbi.c
+++ b/drivers/tty/hvc/hvc_riscv_sbi.c
@@@ -45,15 -44,38 +45,38 @@@ static const struct hv_ops hvc_sbi_v01_
  	.put_chars = hvc_sbi_tty_put,
  };
  
- static int __init hvc_sbi_init(void)
 -static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
++static ssize_t hvc_sbi_dbcn_tty_put(uint32_t vtermno, const u8 *buf, size_t count)
  {
- 	return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
+ 	return sbi_debug_console_write(buf, count);
  }
- device_initcall(hvc_sbi_init);
  
- static int __init hvc_sbi_console_init(void)
 -static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
++static ssize_t hvc_sbi_dbcn_tty_get(uint32_t vtermno, u8 *buf, size_t count)
  {
- 	hvc_instantiate(0, 0, &hvc_sbi_ops);
+ 	return sbi_debug_console_read(buf, count);
+ }
+ 
+ static const struct hv_ops hvc_sbi_dbcn_ops = {
+ 	.put_chars = hvc_sbi_dbcn_tty_put,
+ 	.get_chars = hvc_sbi_dbcn_tty_get,
+ };
+ 
+ static int __init hvc_sbi_init(void)
+ {
+ 	int err;
+ 
+ 	if (sbi_debug_console_available) {
+ 		err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 256));
+ 		if (err)
+ 			return err;
+ 		hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
+ 	} else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
+ 		err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 256));
+ 		if (err)
+ 			return err;
+ 		hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
+ 	} else {
+ 		return -ENODEV;
+ 	}
  
  	return 0;
  }