From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sun, 14 Aug 2022 21:25:31 +0000 (+0200)
Subject: clk: meson: pll: add pcie lock retry workaround
X-Git-Tag: io_uring-6.2-2022-12-19~24^2~2^4^2
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=d73406ed2dcfab7d25493ff3a62dd57f0d9c2bf2;p=linux-block.git

clk: meson: pll: add pcie lock retry workaround

The PCIe PLL locking may be unreliable under some circumstance, such as
high or low temperature. If the PLL fails to lock, reset it a try again.

This helps on the S905X4

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
[commit message amend]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com
---

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index f7b59f7389af..5dfb7d38f452 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -320,12 +320,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
 
 static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
 {
-	meson_clk_pll_init(hw);
+	int retries = 10;
 
-	if (meson_clk_pll_wait_lock(hw))
-		return -EIO;
+	do {
+		meson_clk_pll_init(hw);
+		if (!meson_clk_pll_wait_lock(hw))
+			return 0;
+		pr_info("Retry enabling PCIe PLL clock\n");
+	} while (--retries);
 
-	return 0;
+	return -EIO;
 }
 
 static int meson_clk_pll_enable(struct clk_hw *hw)