From: Cyan Yang Date: Fri, 18 Apr 2025 05:32:36 +0000 (+0800) Subject: dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description X-Git-Tag: v6.16-rc1~18^2~7^2~3 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=d5ca02b25f5dbe44a25afe35cd75d49f1f0b9763;p=linux-block.git dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for matrix multiply accumulate instructions support. Signed-off-by: Cyan Yang Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250418053239.4351-10-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index be203df29eb8..ede6a58ccf53 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -681,6 +681,12 @@ properties: See more details in https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + - const: xsfvfwmaccqqq + description: + SiFive Matrix Multiply Accumulate Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction + # T-HEAD - const: xtheadvector description: