From: Shubhrajyoti Datta Date: Tue, 22 Feb 2022 13:09:02 +0000 (+0530) Subject: clk: zynq: trivial warning fix X-Git-Tag: v5.18-rc1~2^2~3^5~1 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=d583804c97c5ae7a7eba9c44982adcb106c2d160;p=linux-block.git clk: zynq: trivial warning fix Fix the below warning WARNING: Missing a blank line after declarations + int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], Signed-off-by: Shubhrajyoti Datta Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 204b83d911b9..434511dcf5cb 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np) /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), periph_parents, enable);