From: Geert Uytterhoeven Date: Fri, 16 May 2025 13:32:13 +0000 (+0200) Subject: spi: sh-msiof: SITSCR/SIRSCR bitfield conversion X-Git-Tag: v6.16-rc1~23^2~15^2~11 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=c2cc4b72fc14c84fdb1bc49ec98af252ed64fbf3;p=linux-block.git spi: sh-msiof: SITSCR/SIRSCR bitfield conversion Convert MSIOF Transmit and Receive Clock Select Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/f2462c99b6ea2e45b995ab4509c2f039043da032.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 51a9e8936475..9bddf85dd9c7 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -105,15 +105,14 @@ struct sh_msiof_spi_priv { #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ /* SITSCR and SIRSCR */ -#define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */ -#define SISCR_BRPS(i) (((i) - 1) << 8) -#define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ -#define SISCR_BRDV_DIV_2 0 -#define SISCR_BRDV_DIV_4 1 -#define SISCR_BRDV_DIV_8 2 -#define SISCR_BRDV_DIV_16 3 -#define SISCR_BRDV_DIV_32 4 -#define SISCR_BRDV_DIV_1 7 +#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ +#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ +#define SISCR_BRDV_DIV_2 0U +#define SISCR_BRDV_DIV_4 1U +#define SISCR_BRDV_DIV_8 2U +#define SISCR_BRDV_DIV_16 3U +#define SISCR_BRDV_DIV_32 4U +#define SISCR_BRDV_DIV_1 7U /* SICTR */ #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ @@ -299,7 +298,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, t->effective_speed_hz = parent_rate / (brps << div_pow); - scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps); + scr = FIELD_PREP(SISCR_BRDV, sh_msiof_spi_div_array[div_pow]) | + FIELD_PREP(SISCR_BRPS, brps - 1); sh_msiof_write(p, SITSCR, scr); if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SIRSCR, scr);