From: Cyan Yang Date: Fri, 18 Apr 2025 05:32:32 +0000 (+0800) Subject: dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description X-Git-Tag: v6.16-rc1~18^2~7^2~7 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=a5a15e07cbb900b59fbdb927189d24d1d01ad2e7;p=linux-block.git dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for FP32-to-int8 ranged clip instructions support. Signed-off-by: Cyan Yang Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250418053239.4351-6-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index d36e7c68d69a..be203df29eb8 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -675,6 +675,12 @@ properties: See more details in https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + - const: xsfvfnrclipxfqf + description: + SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. + See more details in + https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + # T-HEAD - const: xtheadvector description: