From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 18 Oct 2024 08:39:55 +0000 (+0200)
Subject: arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
X-Git-Tag: v6.13-rc1~140^2~24^2~5
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=8219a455efd4ba11c1d30c1bbc9ce853466c19bf;p=linux-block.git

arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ

When the DSI to eDP bridge was added, pin control for the IRQ pin was
left out, because the pin controller did not support INTC-EX pins yet.

Commit 10544ec1b3436037 ("pinctrl: renesas: r8a779g0: Add INTC-EX
pins, groups, and function") added support for these pins, so add the
missing pin control description.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/89bab2008891be1f003a3c0dbcdf36af3b98da70.1729240573.git.geert+renesas@glider.be
---

diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
index 337ba68342c4..f24814d7c924 100644
--- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
@@ -238,6 +238,9 @@
 	clock-frequency = <400000>;
 
 	bridge@2c {
+		pinctrl-0 = <&irq0_pins>;
+		pinctrl-names = "default";
+
 		compatible = "ti,sn65dsi86";
 		reg = <0x2c>;
 
@@ -341,6 +344,11 @@
 		function = "i2c1";
 	};
 
+	irq0_pins: irq0 {
+		groups = "intc_ex_irq0_a";
+		function = "intc_ex";
+	};
+
 	keys_pins: keys {
 		pins = "GP_5_0", "GP_5_1", "GP_5_2";
 		bias-pull-up;