From: Bjorn Helgaas <bhelgaas@google.com>
Date: Thu, 31 Jul 2025 21:12:16 +0000 (-0500)
Subject: Merge branch 'pci/controller/qcom'
X-Git-Tag: io_uring-6.17-20250815~69^2~6
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=81b3be6cc58a43c9272ca94c9c0f1ce38b3107cb;p=linux-block.git

Merge branch 'pci/controller/qcom'

- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM
  implementation (Mayank Rana)

- Rename gen_pci_init() to pci_host_common_ecam_create() and export for use
  by controller drivers (Mayank Rana)

- Add DT binding and driver support for SA8255p, which supports ECAM for
  Configuration Space access (Mayank Rana)

- Update DT binding and driver to describe PHYs and per-Root Port resets in
  a Root Port stanza and deprecate describing them in the host bridge; this
  makes it possible to support multiple Root Ports in the future (Krishna
  Chaitanya Chundru)

* pci/controller/qcom:
  PCI: qcom: Add support for parsing the new Root Port binding
  dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
  PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
  dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
  PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers
  PCI: dwc: Export DWC MSI controller related APIs
---

81b3be6cc58a43c9272ca94c9c0f1ce38b3107cb
diff --cc drivers/pci/controller/dwc/pcie-designware-host.c
index 101a64187f2a,af6c91ec7312..952f8594b501
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@@ -240,10 -260,12 +240,11 @@@ void dw_pcie_free_msi(struct dw_pcie_r
  							 NULL, NULL);
  	}
  
 -	irq_domain_remove(pp->msi_domain);
  	irq_domain_remove(pp->irq_domain);
  }
+ EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
  
- static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
+ void dw_pcie_msi_init(struct dw_pcie_rp *pp)
  {
  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  	u64 msi_target = (u64)pp->msi_data;