From: Yangbo Lu Date: Tue, 11 Aug 2015 02:53:34 +0000 (+0800) Subject: mmc: sdhci-of-esdhc: add workaround for pre divider initial value X-Git-Tag: v4.3-rc1~46^2~35 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=77bd2f6f6c65b4ad259394d416855ed561f21e8f;p=linux-2.6-block.git mmc: sdhci-of-esdhc: add workaround for pre divider initial value For eSDHC(version < 2.3), the pre divider only could divide base clock by 2 at least. Add workaround for this to avoid unexpected issue. Signed-off-by: Yangbo Lu Acked-by: Joakim Tjernlund Fixes: bd455029d01c ("mmc: sdhci-of-esdhc: Pre divider starts at 1") Signed-off-by: Ulf Hansson --- diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 797be7549a15..653f335bef15 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -208,6 +208,12 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) if (clock == 0) return; + /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ + temp = esdhc_readw(host, SDHCI_HOST_VERSION); + temp = (temp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; + if (temp < VENDOR_V_23) + pre_div = 2; + /* Workaround to reduce the clock frequency for p1010 esdhc */ if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { if (clock > 20000000)