From: Peter Griffin Date: Fri, 26 Apr 2024 12:20:03 +0000 (+0100) Subject: scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata X-Git-Tag: io_uring-6.10-20240523~88^2~4^2~1 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=6f9f0d564b0411f8d86d73c7cb6b2703839e8a96;p=linux-2.6-block.git scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata This allows these registers to be at different offsets or not exist at all on some SoCs variants. Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20240426122004.2249178-6-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker Signed-off-by: Martin K. Petersen --- diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 3ca1357449c3..1e634e271bd8 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -308,8 +308,9 @@ static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; + u32 val = attr->pa_dbg_opt_suite1_val; struct ufs_hba *hba = ufs->hba; - u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite; int i; exynos_ufs_enable_ov_tm(hba); @@ -326,12 +327,13 @@ static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); udelay(1); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + val | (1 << 12)); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); udelay(1600); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); return 0; } @@ -923,14 +925,19 @@ out_exit_phy: static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; struct ufs_hba *hba = ufs->hba; - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), - DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + if (attr->pa_dbg_clk_period_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), ufs->drv_data->uic_attr->tx_trailingclks); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), - ufs->drv_data->uic_attr->pa_dbg_option_suite); + + if (attr->pa_dbg_opt_suite1_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + attr->pa_dbg_opt_suite1_val); } static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) @@ -1487,10 +1494,11 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba) static int fsd_ufs_pre_link(struct exynos_ufs *ufs) { - int i; + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; struct ufs_hba *hba = ufs->hba; + int i; - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); @@ -1514,7 +1522,9 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs) ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183); + + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + 0x2e820183); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); exynos_ufs_establish_connt(ufs); @@ -1656,7 +1666,9 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = { .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), - .pa_dbg_option_suite = 0x30103, + .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val = 0x30103, + .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, }; static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { @@ -1730,7 +1742,9 @@ static struct exynos_ufs_uic_attr fsd_uic_attr = { .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), - .pa_dbg_option_suite = 0x2E820183, + .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val = 0x2E820183, + .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, }; static const struct exynos_ufs_drv_data fsd_ufs_drvs = { diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 7acc13914100..f30423223474 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -145,7 +145,11 @@ struct exynos_ufs_uic_attr { /* Common Attributes */ unsigned int cmn_pwm_clk_ctrl; /* Internal Attributes */ - unsigned int pa_dbg_option_suite; + unsigned int pa_dbg_clk_period_off; + unsigned int pa_dbg_opt_suite1_val; + unsigned int pa_dbg_opt_suite1_off; + unsigned int pa_dbg_opt_suite2_val; + unsigned int pa_dbg_opt_suite2_off; /* Changeable Attributes */ unsigned int rx_adv_fine_gran_sup_en; unsigned int rx_adv_fine_gran_step;