From: Ben Widawsky Date: Fri, 11 Jun 2021 19:01:11 +0000 (-0700) Subject: cxl/hdm: Fix decoder count calculation X-Git-Tag: v5.14-rc1~84^2~10 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=6423035fd26c1ecb72f90ecab909e9afa36942b8;p=linux-2.6-block.git cxl/hdm: Fix decoder count calculation The decoder count in the HDM decoder capability structure is an encoded field. As defined in the spec: Decoder Count: Reports the number of memory address decoders implemented by the component. 0 – 1 Decoder 1 – 2 Decoders 2 – 4 Decoders 3 – 6 Decoders 4 – 8 Decoders 5 – 10 Decoders All other values are reserved Nothing is actually fixed by this as nothing actually used this mapping yet. Cc: Ira Weiny Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") Acked-by: Jonathan Cameron Signed-off-by: Ben Widawsky Link: https://lore.kernel.org/r/20210611190111.121295-1-ben.widawsky@intel.com Signed-off-by: Dan Williams --- diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index 1b9ee0b08384..b134b29923ca 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -595,7 +595,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, hdr = readl(register_block); - decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr); + decoder_cnt = cxl_hdm_decoder_count(hdr); length = 0x20 * decoder_cnt + 0x10; map->hdm_decoder.valid = true; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b988ea288f53..97a273ae3947 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -41,6 +41,13 @@ #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c #define CXL_HDM_DECODER0_CTRL_OFFSET 0x20 +static inline int cxl_hdm_decoder_count(u32 cap_hdr) +{ + int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); + + return val ? val * 2 : 1; +} + /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 #define CXLDEV_CAP_ARRAY_CAP_ID 0