From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Tue, 8 Feb 2022 15:35:24 +0000 (+0530)
Subject: arm64: dts: qcom: ipq8074: enable the GICv2m support
X-Git-Tag: v5.18-rc1~145^2~14^2~25
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=59892de947f0ca1d65426f7a6c6e258863fa65d7;p=linux-2.6-block.git

arm64: dts: qcom: ipq8074: enable the GICv2m support

GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
---

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 27624f5a56ba..642f9e71dbcf 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -634,9 +634,18 @@
 
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
+			#address-cells = <1>;
+			#size-cells = <1>;
 			interrupt-controller;
 			#interrupt-cells = <0x3>;
 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+			ranges = <0 0xb00a000 0xffd>;
+
+			v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				msi-controller;
+				reg = <0x0 0xffd>;
+			};
 		};
 
 		timer {