From: Ville Syrjälä Date: Fri, 18 Aug 2017 18:37:02 +0000 (+0300) Subject: drm/i915: Gen3 HWSTAM is actually 32 bits X-Git-Tag: v4.15-rc1~19^2~50^2~80 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=5190707e7a4fc701e94cd7e152d15dbba90b63ff;p=linux-block.git drm/i915: Gen3 HWSTAM is actually 32 bits Bspec claims that HWSTAM is only 16 bits on gen3, but the other interrupts registers are 32 bits and there are 18 valid interrupt bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the bits, so it seems the spec is incorrect about the size of the register. And indeed I can clear bits 16 and 17 just fine with a 32 bit write. So let's adjust the code to treat the register as 32 bits. Acked-by: Chris Wilson Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-14-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 26569a00b40c..003a92857102 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3755,7 +3755,7 @@ static void i915_irq_preinstall(struct drm_device * dev) i9xx_pipestat_irq_reset(dev_priv); - I915_WRITE16(HWSTAM, 0xeffe); + I915_WRITE(HWSTAM, 0xffffeffe); GEN3_IRQ_RESET(); } @@ -3862,7 +3862,7 @@ static void i915_irq_uninstall(struct drm_device * dev) i9xx_pipestat_irq_reset(dev_priv); - I915_WRITE16(HWSTAM, 0xffff); + I915_WRITE(HWSTAM, 0xffffffff); GEN3_IRQ_RESET(); }