From: Vasily Khoruzhick Date: Tue, 18 Mar 2025 18:18:51 +0000 (-0700) Subject: clk: rockchip: rk3568: Add PLL rate for 33.3MHz X-Git-Tag: v6.16-rc1~114^2^4^2~15 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=3cb09de48f652abd662b436b23f914d3eb66f1fd;p=linux-2.6-block.git clk: rockchip: rk3568: Add PLL rate for 33.3MHz Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native mode of 800x480 Signed-off-by: Vasily Khoruzhick Link: https://lore.kernel.org/r/20250318181930.1178256-1-anarsoul@gmail.com Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 7d9279291e76..ed2fb08bd39d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0), { /* sentinel */ }, };