From: Heiko Carstens Date: Sat, 3 Feb 2024 10:44:57 +0000 (+0100) Subject: s390/fpu: fix VLGV macro X-Git-Tag: block-6.9-20240315~48^2~66 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=39ceca158802f0891805f4e4e6724716294d36f2;p=linux-2.6-block.git s390/fpu: fix VLGV macro The VLGV macro generates the VLGV instruction and has a vr parameter which correlates to the V3 vector register field of the instruction (bits 12-15). Due to its position in the VRS-c instruction format of the VLGV instruction, this field correlates to the second bit of the RXB byte of the instruction (see Principles of Operation, Chapter "Vector Overview and Support Instructions"). Within the VLGV macro the MRXBOPC macro is used to generate the RXB field of the instruction. The usage of the MRXBOPC macro is incorrect, since the vector register number is passed as third parameter (which correlates to the first bit of the RXB byte), while it should be passed as fourth parameter (second bit of the RXB byte). In result an incorrect instruction would be generated if the VLGV macro would be used for vector register numbers larger than 15. Fix this and pass the vector register number as fourth parameter. Currently there are no users within the kernel which use the macro in a way that broken code would be generated. Reviewed-by: Jens Remus Reviewed-by: Claudio Imbrenda Reviewed-by: Hendrik Brueckner Signed-off-by: Heiko Carstens --- diff --git a/arch/s390/include/asm/vx-insn-asm.h b/arch/s390/include/asm/vx-insn-asm.h index 360f8b36d962..d01be91e228b 100644 --- a/arch/s390/include/asm/vx-insn-asm.h +++ b/arch/s390/include/asm/vx-insn-asm.h @@ -350,7 +350,7 @@ VX_NUM v3, \vr .word 0xE700 | (r1 << 4) | (v3&15) .word (b2 << 12) | (\disp) - MRXBOPC \m, 0x21, v3 + MRXBOPC \m, 0x21, 0, v3 .endm .macro VLGVB gr, vr, disp, base="%r0" VLGV \gr, \vr, \disp, \base, 0