From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 21 Nov 2022 10:53:45 +0000 (+0100)
Subject: Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux... 
X-Git-Tag: io_uring-6.2-2022-12-19~116^2~30
X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=2092ad3a79ca6d987f994e8b9b72f9fde5f29aa8;p=linux-block.git

Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt

Renesas RISC-V DT updates for v6.2

  - Add initial support for the Renesas RZ/Five SoC and the Renesas
    RZ/Five SMARC EVK development board.

* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
  riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
  MAINTAINERS: Add entry for Renesas RISC-V
  riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
  riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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2092ad3a79ca6d987f994e8b9b72f9fde5f29aa8