From: Ville Syrjälä Date: Mon, 20 May 2024 17:14:59 +0000 (+0300) Subject: drm/i915: Add separate define for SEL_FETCH_CUR_CTL() X-Git-Tag: io_uring-6.11-20240722~49^2~20^2~272 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=199bc8c175d712be1610dcad7f7240ad5c864281;p=linux-block.git drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Split the cursor stuff from the rest of the selective fetch plane registers so that we can collect all cursor registers in intel_cursor_regs.h. Also take the opportunity to rename the registers to match the spec. v2: Pass the correct register offset fpr pipe B (Jani) s/mtl+/tgl+/ as that's where this was introduced Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents actually match the normal CUR_CTL register Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240520171459.9661-1-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index c780ce146131..b44809899502 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane, if (!crtc_state->enable_psr2_sel_fetch) return; - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0); } static void wa_16021440873(struct intel_plane *plane, @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane, ctl &= ~MCURSOR_MODE_MASK; ctl |= MCURSOR_MODE_64_2B; - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl); + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), PIPESRC_HEIGHT(et_y_position)); @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, val); } - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); } else { /* Wa_16021440873 */ diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 270c26c2e6df..e58930ff32ea 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -95,4 +95,9 @@ #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) +/* tgl+ */ +#define _SEL_FETCH_CUR_CTL_A 0x70880 +#define _SEL_FETCH_CUR_CTL_B 0x71880 +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B) + #endif /* __INTEL_CURSOR_REGS_H__ */