From: Lad Prabhakar Date: Thu, 17 Jun 2021 15:54:32 +0000 (+0100) Subject: clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() X-Git-Tag: libata-5.15-2021-09-05~6^2~3^2~1^2~13 X-Git-Url: https://git.kernel.dk/?a=commitdiff_plain;h=1606e81543f80fc3b1912957cf6d8fa62e40b8e5;p=linux-block.git clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() Fix clock index out of range check for module clocks in rzg2l_cpg_clk_src_twocell_get(). Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Reported-by: Dan Carpenter Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c index 34e90ee46290..9addc9dae31a 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.c +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -222,7 +222,7 @@ static struct clk case CPG_MOD: type = "module"; - if (clkidx > priv->num_mod_clks) { + if (clkidx >= priv->num_mod_clks) { dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL);