irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
authorConor Dooley <conor.dooley@microchip.com>
Fri, 18 Nov 2022 10:42:59 +0000 (10:42 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 8 Dec 2022 23:57:06 +0000 (15:57 -0800)
The SiFive PLIC driver is used by all current implementations, including
those that do not have a SiFive PLIC. The current driver supports more
than just SiFive PLICs at present and, where possible, future PLIC
implementations will also use this driver. As every supported RISC-V SoC
selects the driver directly in Kconfig.socs there's no point in exposing
this kconfig option to users.

The Kconfig help text, in its current form, is misleading. There's no
point doing anything about that though, as it will no longer be user
selectable. Remove it.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221118104300.85016-2-conor@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
drivers/irqchip/Kconfig

index 7ef9f5e696d317415c30b258f637db95c1fcaf81..ecb3e3119d2e15788b010cd7726d53a9aec5f93f 100644 (file)
@@ -551,18 +551,10 @@ config RISCV_INTC
           If you don't know what to do here, say Y.
 
 config SIFIVE_PLIC
-       bool "SiFive Platform-Level Interrupt Controller"
+       bool
        depends on RISCV
        select IRQ_DOMAIN_HIERARCHY
        select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
-       help
-          This enables support for the PLIC chip found in SiFive (and
-          potentially other) RISC-V systems.  The PLIC controls devices
-          interrupts and connects them to each core's local interrupt
-          controller.  Aside from timer and software interrupts, all other
-          interrupt sources are subordinate to the PLIC.
-
-          If you don't know what to do here, say Y.
 
 config EXYNOS_IRQ_COMBINER
        bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST