unsigned int hygon_genuine;
unsigned int max_level, max_extended_level;
unsigned int has_invariant_tsc;
-unsigned int do_nhm_platform_info;
unsigned int aperf_mperf_multiplier = 1;
double bclk;
double base_hz;
struct platform_features {
bool has_msr_misc_feature_control; /* MSR_MISC_FEATURE_CONTROL */
bool has_msr_misc_pwr_mgmt; /* MSR_MISC_PWR_MGMT */
+ bool has_nhm_msrs; /* MSR_PLATFORM_INFO, MSR_IA32_TEMPERATURE_TARGET, MSR_SMI_COUNT, MSR_PKG_CST_CONFIG_CONTROL, TRL MSRs */
int bclk_freq; /* CPU base clock */
int cst_limit; /* MSR_PKG_CST_CONFIG_CONTROL */
};
static const struct platform_features nhm_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_133MHZ,
.cst_limit = CST_LIMIT_NHM,
};
static const struct platform_features nhx_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_133MHZ,
.cst_limit = CST_LIMIT_NHM,
};
static const struct platform_features snb_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SNB,
};
static const struct platform_features snx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SNB,
};
static const struct platform_features ivb_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SNB,
};
static const struct platform_features ivx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SNB,
};
static const struct platform_features hsw_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features hsx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features hswl_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features hswg_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features bdw_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features bdwg_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features bdx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features skl_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features cnl_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_HSW,
};
static const struct platform_features skx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SKX,
};
static const struct platform_features icx_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_ICX,
};
static const struct platform_features spr_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_SKX,
};
static const struct platform_features slv_features = {
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_SLV,
.cst_limit = CST_LIMIT_SLV,
};
static const struct platform_features slvd_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_SLV,
.cst_limit = CST_LIMIT_SLV,
};
static const struct platform_features amt_features = {
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_133MHZ,
.cst_limit = CST_LIMIT_AMT,
};
static const struct platform_features gmt_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_GMT,
};
static const struct platform_features gmtd_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_GMT,
};
static const struct platform_features gmtp_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_GMT,
};
static const struct platform_features tmt_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_GMT,
};
static const struct platform_features tmtd_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_GMT,
};
static const struct platform_features knl_features = {
.has_msr_misc_pwr_mgmt = 1,
+ .has_nhm_msrs = 1,
.bclk_freq = BCLK_100MHZ,
.cst_limit = CST_LIMIT_KNL,
};
unsigned long long msr;
int *pkg_cstate_limits;
- if (!do_nhm_platform_info)
+ if (!platform->has_nhm_msrs)
return;
switch (platform->cst_limit) {
unsigned long long msr;
unsigned int base_ratio;
- if (!do_nhm_platform_info)
+ if (!platform->has_nhm_msrs)
return;
if (platform->bclk_freq == BCLK_100MHZ)
has_base_hz = 1;
}
-/*
- * NHM adds support for additional MSRs:
- *
- * MSR_SMI_COUNT 0x00000034
- *
- * MSR_PLATFORM_INFO 0x000000ce
- * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
- *
- * MSR_MISC_PWR_MGMT 0x000001aa
- *
- * MSR_PKG_C3_RESIDENCY 0x000003f8
- * MSR_PKG_C6_RESIDENCY 0x000003f9
- * MSR_CORE_C3_RESIDENCY 0x000003fc
- * MSR_CORE_C6_RESIDENCY 0x000003fd
- */
-int probe_nhm_msrs(unsigned int family, unsigned int model)
-{
- if (!genuine_intel)
- return 0;
-
- if (family != 6)
- return 0;
-
- switch (model) {
- case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
- case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
- case INTEL_FAM6_SANDYBRIDGE: /* SNB */
- case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
- case INTEL_FAM6_IVYBRIDGE: /* IVB */
- case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
- case INTEL_FAM6_HASWELL: /* HSW */
- case INTEL_FAM6_HASWELL_G: /* HSW */
- case INTEL_FAM6_HASWELL_X: /* HSX */
- case INTEL_FAM6_HASWELL_L: /* HSW */
- case INTEL_FAM6_BROADWELL: /* BDW */
- case INTEL_FAM6_BROADWELL_G: /* BDW */
- case INTEL_FAM6_BROADWELL_X: /* BDX */
- case INTEL_FAM6_SKYLAKE_L: /* SKL */
- case INTEL_FAM6_CANNONLAKE_L: /* CNL */
- case INTEL_FAM6_SKYLAKE_X: /* SKX */
- case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
- case INTEL_FAM6_ICELAKE_X: /* ICX */
- case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
- case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
- case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
- case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
- case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
- case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
- case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
- case INTEL_FAM6_ATOM_TREMONT: /* EHL */
- case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
/*
* SLV client has support for unique MSRs:
*
static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
{
- if (!do_nhm_platform_info)
+ if (!platform->has_nhm_msrs)
return;
dump_nhm_platform_info();
}
/* Temperature Target MSR is Nehalem and newer only */
- if (!do_nhm_platform_info)
+ if (!platform->has_nhm_msrs)
goto guess;
if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
{
unsigned long long msr;
- if (!do_nhm_platform_info)
+ if (!platform->has_nhm_msrs)
return;
if (!platform->has_msr_misc_pwr_mgmt)
BIC_PRESENT(BIC_TSC_MHz);
probe_cst_limit();
- if (probe_nhm_msrs(family, model)) {
- do_nhm_platform_info = 1;
+ if (platform->has_nhm_msrs) {
BIC_PRESENT(BIC_CPU_c1);
BIC_PRESENT(BIC_CPU_c3);
BIC_PRESENT(BIC_CPU_c6);