drm/amdgpu/gfx8: KIQ is also disabled when MEC is disabled
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 17:03:07 +0000 (13:03 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 6 Apr 2017 17:26:47 +0000 (13:26 -0400)
Set the ready flag to reflect this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index e0fa0d30e162a0fbe4fa24821b4b0765920ba5a4..2e0f5563557936bacb2ac0ea9f1d85bed5d221c8 100644 (file)
@@ -4565,6 +4565,7 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
                for (i = 0; i < adev->gfx.num_compute_rings; i++)
                        adev->gfx.compute_ring[i].ready = false;
+               adev->gfx.kiq.ring.ready = false;
        }
        udelay(50);
 }