ARM: dts: r8a7793: Add SDHI controllers
authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Mon, 18 Apr 2016 16:02:56 +0000 (18:02 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 25 Apr 2016 04:10:10 +0000 (14:10 +1000)
Same as on r8a7791.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7793.dtsi

index bddc31283bd93c4b4062cf415d7c9305b557de41..6186179fd66db6b2bfef88650efd5cb904663f50 100644 (file)
                reg = <0 0xe6060000 0 0x250>;
        };
 
+       sdhi0: sd@ee100000 {
+               compatible = "renesas,sdhi-r8a7793";
+               reg = <0 0xee100000 0 0x328>;
+               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
+               dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
+               dma-names = "tx", "rx";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
+
+       sdhi1: sd@ee140000 {
+               compatible = "renesas,sdhi-r8a7793";
+               reg = <0 0xee140000 0 0x100>;
+               interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
+               dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
+               dma-names = "tx", "rx";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
+
+       sdhi2: sd@ee160000 {
+               compatible = "renesas,sdhi-r8a7793";
+               reg = <0 0xee160000 0 0x100>;
+               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
+               dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
+               dma-names = "tx", "rx";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
+
        scifa0: serial@e6c40000 {
                compatible = "renesas,scifa-r8a7793",
                             "renesas,rcar-gen2-scifa", "renesas,scifa";