drm/amdgpu/userq: rework driver parameter
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 14 Apr 2025 18:18:03 +0000 (14:18 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 21 Apr 2025 14:55:47 +0000 (10:55 -0400)
Replace disable_kq parameter with user_queue parameter.
The parameter has the following logic:
 -1 = auto (ASIC specific default)
  0 = user queues disabled
  1 = user queues enabled and kernel queues enabled (if supported)
  2 = user queues enabled and kernel queues disabled

The default behavior (-1) is currently the same as 0 for current
ASICs.  To enable user queues (in addition to kernel queues) set
user_queue=1. To enable user queues and disable kernel queues
(to make all resources available to user queues), set user_queue=2.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

index b156e31ac86ac8ece5f52ecb37e80dcededd287f..3212fd78b012911e97203bb0816129bb015b6db8 100644 (file)
@@ -271,7 +271,7 @@ extern int amdgpu_agp;
 extern int amdgpu_rebar;
 
 extern int amdgpu_wbrf;
-extern int amdgpu_disable_kq;
+extern int amdgpu_user_queue;
 
 #define AMDGPU_VM_MAX_NUM_CTX                  4096
 #define AMDGPU_SG_THRESHOLD                    (256*1024*1024)
index a117cd95b9dcde239d198c30cb596139526781e9..e24b0c730baf52cc20aa0103d552ad79fdc5ead5 100644 (file)
@@ -242,7 +242,7 @@ int amdgpu_wbrf = -1;
 int amdgpu_damage_clips = -1; /* auto */
 int amdgpu_umsch_mm_fwlog;
 int amdgpu_rebar = -1; /* auto */
-int amdgpu_disable_kq = -1;
+int amdgpu_user_queue = -1;
 
 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
                        "DRM_UT_CORE",
@@ -1114,12 +1114,15 @@ MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = en
 module_param_named(rebar, amdgpu_rebar, int, 0444);
 
 /**
- * DOC: disable_kq (int)
- * Disable kernel queues on systems that support user queues.
- * (0 = kernel queues enabled, 1 = kernel queues disabled, -1 = auto (default setting))
+ * DOC: user_queue (int)
+ * Enable user queues on systems that support user queues.
+ * -1 = auto (ASIC specific default)
+ *  0 = user queues disabled
+ *  1 = user queues enabled and kernel queues enabled (if supported)
+ *  2 = user queues enabled and kernel queues disabled
  */
-MODULE_PARM_DESC(disable_kq, "Disable kernel queues (-1 = auto (default), 0 = enable KQ, 1 = disable KQ)");
-module_param_named(disable_kq, amdgpu_disable_kq, int, 0444);
+MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
+module_param_named(user_queue, amdgpu_user_queue, int, 0444);
 
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
index caaddab31023f651bba87c1c6499c6dcbd0d92d9..91dd365cb1e6c0242809ada46b542918f1f756ef 100644 (file)
@@ -487,6 +487,7 @@ struct amdgpu_gfx {
        struct mutex                    workload_profile_mutex;
 
        bool                            disable_kq;
+       bool                            disable_uq;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
index a6c8f07a0da4be094bb48d179842c7c547826bd0..59778b978eb57271ee061b776afc3753972cc195 100644 (file)
@@ -138,6 +138,7 @@ struct amdgpu_sdma {
        uint32_t                supported_reset;
        struct list_head        reset_callback_list;
        bool                    no_user_submission;
+       bool                    disable_uq;
 };
 
 /*
index a528afe38e0b6bbdd1b9e064f5c89c6b783c5fba..70c38e53e691846e25c7d6f923974ed04416dcf8 100644 (file)
@@ -1632,7 +1632,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 0, 3):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
@@ -1646,7 +1646,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 3):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
@@ -5211,8 +5211,22 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = true;
+               break;
+       case 1:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = false;
+               break;
+       case 2:
                adev->gfx.disable_kq = true;
+               adev->gfx.disable_uq = false;
+               break;
+       }
 
        adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
 
index 4c8958f91edaed3127d67681e8b418f30761320b..1523f5b352c71bb9d02166b5eca45448eba27712 100644 (file)
@@ -1418,7 +1418,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(12, 0, 1):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
@@ -3819,8 +3819,22 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = true;
+               break;
+       case 1:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = false;
+               break;
+       case 2:
                adev->gfx.disable_kq = true;
+               adev->gfx.disable_uq = false;
+               break;
+       }
 
        adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
 
index c3d53974e7f53bbd54f13c61b7b99048c12e1152..6bb36187a53dcd7d8ba4e896ed3c6322691da921 100644 (file)
@@ -1269,8 +1269,22 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        int r;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = true;
+               break;
+       case 1:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = false;
+               break;
+       case 2:
                adev->sdma.no_user_submission = true;
+               adev->sdma.disable_uq = false;
+               break;
+       }
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);
        if (r)
@@ -1351,7 +1365,7 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
        /* add firmware version checks here */
-       if (0)
+       if (0 && !adev->sdma.disable_uq)
                adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif
        r = amdgpu_sdma_sysfs_reset_mask_init(adev);
index e1a6b153385068e2a890f8113fb56f9f56d0206b..943c6446a0a736c1735afc290dc055c5041f8ba8 100644 (file)
@@ -1254,8 +1254,22 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        int r;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = true;
+               break;
+       case 1:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = false;
+               break;
+       case 2:
                adev->sdma.no_user_submission = true;
+               adev->sdma.disable_uq = false;
+               break;
+       }
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);
        if (r) {
@@ -1326,7 +1340,7 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
        /* add firmware version checks here */
-       if (0)
+       if (0 && !adev->sdma.disable_uq)
                adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif