net: phy: realtek: add defines for shadowed c45 standard registers

Realtek shadows standard c45 registers in VEND2 device register space.
Add defines for these VEND2 registers, based on the names of the
standard c45 registers.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/c90bdf76-f8b8-4d06-9656-7a52d5658ee6@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
index b877057348d55100bb46fd27134f54c381455be2..7a0b19d66acace907b8d0e2143cb686894bd8707 100644 (file)
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -94,6 +94,16 @@
 #define RTL_VND2_PHYSR_MASTER                  BIT(11)
 #define RTL_VND2_PHYSR_SPEED_MASK              (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
 
+#define        RTL_MDIO_PCS_EEE_ABLE                   0xa5c4
+#define        RTL_MDIO_AN_EEE_ADV                     0xa5d0
+#define        RTL_MDIO_AN_EEE_LPABLE                  0xa5d2
+#define        RTL_MDIO_AN_10GBT_CTRL                  0xa5d4
+#define        RTL_MDIO_AN_10GBT_STAT                  0xa5d6
+#define        RTL_MDIO_PMA_SPEED                      0xa616
+#define        RTL_MDIO_AN_EEE_LPABLE2                 0xa6d0
+#define        RTL_MDIO_AN_EEE_ADV2                    0xa6d4
+#define        RTL_MDIO_PCS_EEE_ABLE2                  0xa6ec
+
 #define RTL_GENERIC_PHYID                      0x001cc800
 #define RTL_8211FVD_PHYID                      0x001cc878
 #define RTL_8221B                              0x001cc840
@@ -751,11 +761,11 @@ static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
        if (devnum == MDIO_MMD_VEND2)
                ret = rtlgen_read_vend2(phydev, regnum);
        else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
-               ret = rtlgen_read_vend2(phydev, 0xa5c4);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE);
        else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
-               ret = rtlgen_read_vend2(phydev, 0xa5d0);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV);
        else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
-               ret = rtlgen_read_vend2(phydev, 0xa5d2);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE);
        else
                ret = -EOPNOTSUPP;
 
@@ -770,7 +780,7 @@ static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
        if (devnum == MDIO_MMD_VEND2)
                ret = rtlgen_write_vend2(phydev, regnum, val);
        else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
-               ret = rtlgen_write_vend2(phydev, regnum, 0xa5d0);
+               ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV);
        else
                ret = -EOPNOTSUPP;
 
@@ -785,11 +795,11 @@ static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
                return ret;
 
        if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
-               ret = rtlgen_read_vend2(phydev, 0xa6ec);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2);
        else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
-               ret = rtlgen_read_vend2(phydev, 0xa6d4);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2);
        else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
-               ret = rtlgen_read_vend2(phydev, 0xa6d0);
+               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2);
 
        return ret;
 }
@@ -803,7 +813,7 @@ static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
                return ret;
 
        if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
-               ret = rtlgen_write_vend2(phydev, 0xa6d4, val);
+               ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val);
 
        return ret;
 }
@@ -899,7 +909,7 @@ static int rtl822x_get_features(struct phy_device *phydev)
 {
        int val;
 
-       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa616);
+       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED);
        if (val < 0)
                return val;
 
@@ -920,7 +930,8 @@ static int rtl822x_config_aneg(struct phy_device *phydev)
        if (phydev->autoneg == AUTONEG_ENABLE) {
                u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 
-               ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xa5d4,
+               ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
+                                            RTL_MDIO_AN_10GBT_CTRL,
                                             MDIO_AN_10GBT_CTRL_ADV2_5G |
                                             MDIO_AN_10GBT_CTRL_ADV5G, adv);
                if (ret < 0)
@@ -966,7 +977,7 @@ static int rtl822x_read_status(struct phy_device *phydev)
            !phydev->autoneg_complete)
                return 0;
 
-       lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa5d6);
+       lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT);
        if (lpadv < 0)
                return lpadv;