drm/amdgpu: add sdma 7.0 support for copy dcc buffer
authorFrank Min <Frank.Min@amd.com>
Wed, 10 Apr 2024 13:40:16 +0000 (21:40 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 14 Jun 2024 19:22:14 +0000 (15:22 -0400)
1. Add dcc buffer flag for copy buffer
2. Add sdma 7.0 support copy dcc buffer

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

index f09f33d1beec350d4cdac5ab9c6ade1c03be4205..9a92dd3c9fb83081f30126aba1c09432e057d99c 100644 (file)
@@ -295,8 +295,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
        struct amdgpu_res_cursor src_mm, dst_mm;
        struct dma_fence *fence = NULL;
        int r = 0;
-
        uint32_t copy_flags = 0;
+       struct amdgpu_bo *abo_src, *abo_dst;
 
        if (!adev->mman.buffer_funcs_enabled) {
                DRM_ERROR("Trying to move memory with ring turned off.\n");
@@ -325,8 +325,14 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                if (r)
                        goto error;
 
+               abo_src = ttm_to_amdgpu_bo(src->bo);
+               abo_dst = ttm_to_amdgpu_bo(dst->bo);
                if (tmz)
                        copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
+               if (abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+                       copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
+               if (abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+                       copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
 
                r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
                                       &next, false, true, copy_flags);
index 53d5a5990c3110d6c1e7bd50ad3a6d3e77dd60d4..7c903a6c9ddb414b42e673bd354de15428cc2a53 100644 (file)
@@ -112,6 +112,8 @@ struct amdgpu_copy_mem {
 };
 
 #define AMDGPU_COPY_FLAGS_TMZ          (1 << 0)
+#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED    (1 << 1)
+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED     (1 << 2)
 
 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
@@ -148,7 +150,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_fini(struct amdgpu_device *adev);
 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
                                        bool enable);
-
 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
                       uint64_t dst_offset, uint32_t byte_count,
                       struct dma_resv *resv,
index 6af23e7888ca82a7c3d007ec7a2c9b2f7641ea50..d8cf830916b9767b3c12c4bbd31feee10f96fc7d 100644 (file)
 #define SDMA_GCR_GLM_WB                        (1 << 4)
 #define SDMA_GCR_GL1_RANGE(x)          (((x) & 0x3) << 2)
 #define SDMA_GCR_GLI_INV(x)            (((x) & 0x3) << 0)
+
+#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f)
+#define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9)
+#define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16)
+#define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18)
+#define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24)
+#define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26)
+
 /*
 ** Definitions for SDMA_PKT_COPY_LINEAR packet
 */
index ab1dea77be6e7e60bf4c69e5df69e6abcef7cf12..96514fd77e3558318b7e028c29898a3a7ec643ff 100644 (file)
@@ -1568,13 +1568,22 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
 {
        ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
                SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
-               SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
+               SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |
+               SDMA_PKT_COPY_LINEAR_HEADER_CPV((copy_flags &
+                       (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)) ? 1 : 0);
+
        ib->ptr[ib->length_dw++] = byte_count - 1;
        ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
        ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
        ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
        ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
        ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
+
+       if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
+               ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(4) | SDMA_DCC_NUM_TYPE(4) |
+                       ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
+                       ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
+                       SDMA_DCC_MAX_COM(1) | SDMA_DCC_MAX_UCOM(1);
 }
 
 /**
@@ -1603,7 +1612,6 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
        .copy_max_bytes = 0x400000,
        .copy_num_dw = 7,
        .emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
-
        .fill_max_bytes = 0x400000,
        .fill_num_dw = 5,
        .emit_fill_buffer = sdma_v7_0_emit_fill_buffer,