ASoC: AMD: Send correct channel for configuring DMA descriptors
authorAgrawal, Akshu <Akshu.Agrawal@amd.com>
Mon, 16 Jul 2018 07:02:40 +0000 (15:02 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 16 Jul 2018 14:30:11 +0000 (15:30 +0100)
Earlier, ch1 was used to define ACP-SYSMEM transfer and ch2 for
ACP-I2S transfer. With recent patches ch1 is used to define channel
order number 1 and ch2 as channel order number 2. Thus,
Playback:
ch1:SYSMEM->ACP
ch2:ACP->I2S
Capture:
ch1:I2S->ACP
ch1:ACP->SYSMEM

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/amd/acp-pcm-dma.c

index 65c1033bd51cc3ae5d921e61254f7c56843f8c5e..eeb86776725248f7f9b94acccd3d92e191fece70 100644 (file)
@@ -322,17 +322,27 @@ static void config_acp_dma(void __iomem *acp_mmio,
                           struct audio_substream_data *rtd,
                           u32 asic_type)
 {
+       u16 ch_acp_sysmem, ch_acp_i2s;
+
        acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
                       rtd->pte_offset);
+
+       if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
+               ch_acp_sysmem = rtd->ch1;
+               ch_acp_i2s = rtd->ch2;
+       } else {
+               ch_acp_i2s = rtd->ch1;
+               ch_acp_sysmem = rtd->ch2;
+       }
        /* Configure System memory <-> ACP SRAM DMA descriptors */
        set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
                                       rtd->direction, rtd->pte_offset,
-                                      rtd->ch1, rtd->sram_bank,
+                                      ch_acp_sysmem, rtd->sram_bank,
                                       rtd->dma_dscr_idx_1, asic_type);
        /* Configure ACP SRAM <-> I2S DMA descriptors */
        set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
                                       rtd->direction, rtd->sram_bank,
-                                      rtd->destination, rtd->ch2,
+                                      rtd->destination, ch_acp_i2s,
                                       rtd->dma_dscr_idx_2, asic_type);
 }
 
@@ -995,16 +1005,24 @@ static int acp_dma_prepare(struct snd_pcm_substream *substream)
 {
        struct snd_pcm_runtime *runtime = substream->runtime;
        struct audio_substream_data *rtd = runtime->private_data;
+       u16 ch_acp_sysmem, ch_acp_i2s;
 
        if (!rtd)
                return -EINVAL;
 
+       if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
+               ch_acp_sysmem = rtd->ch1;
+               ch_acp_i2s = rtd->ch2;
+       } else {
+               ch_acp_i2s = rtd->ch1;
+               ch_acp_sysmem = rtd->ch2;
+       }
        config_acp_dma_channel(rtd->acp_mmio,
-                              rtd->ch1,
+                              ch_acp_sysmem,
                               rtd->dma_dscr_idx_1,
                               NUM_DSCRS_PER_CHANNEL, 0);
        config_acp_dma_channel(rtd->acp_mmio,
-                              rtd->ch2,
+                              ch_acp_i2s,
                               rtd->dma_dscr_idx_2,
                               NUM_DSCRS_PER_CHANNEL, 0);
        return 0;