octeontx2-af: Enable transmit side LBK link

For enabling VF-VF switching the packets egressing
out of CGX mapped VFs needed to be sent to LBK
so that same packets are received back to the system.
But the LBK link also needs to be enabled in addition
to a VF's mapped CGX_LMAC link otherwise hardware
raises send error interrupt indicating selected LBK
link is not enabled in NIX_AF_TL3_TL2X_LINKX_CFG register.
Hence this patch enables all LBK links in
TL3_TL2_LINKX_CFG registers.
Also to enable packet flow between PFs/VFs of NIX0
to PFs/VFs of NIX1(in 98xx silicon) the NPC TX DMAC
rules has to be installed such that rules must be hit
for any TX interface i.e., NIX0-TX or NIX1-TX provided
DMAC match creteria is met. Hence this patch changes the
behavior such that MCAM is programmed to match with any
NIX0/1-TX interface for TX rules.

Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 10cddf1ac7b9efa7bde20809ddc6886e58c87d3c..086eb6d283ee43d9a0d80fe82b9e5c5cfb2846c7 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -2859,6 +2859,12 @@ static int rvu_enable_sriov(struct rvu *rvu)
        if (!vfs)
                return 0;
 
+       /* LBK channel number 63 is used for switching packets between
+        * CGX mapped VFs. Hence limit LBK pairs till 62 only.
+        */
+       if (vfs > 62)
+               vfs = 62;
+
        /* Save VFs number for reference in VF interrupts handlers.
         * Since interrupts might start arriving during SRIOV enablement
         * ordinary API cannot be used to get number of enabled VFs.

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 10e58a5d5861acfd3344d4020822e0eefd2f5674..e53f530e5e319645860b2ee1f59c98b053e4ef5c 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -415,6 +415,8 @@ struct npc_kpu_profile_adapter {
        size_t                          kpus;
 };
 
+#define RVU_SWITCH_LBK_CHAN    63
+
 struct rvu {
        void __iomem            *afreg_base;
        void __iomem            *pfreg_base;

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index aeae377044280759f046a605f166acd8745a0146..a2d69eaac4f88275a02503ae65ce9097397cb9da 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1952,6 +1952,35 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
        pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE);
 }
 
+static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,
+                              u16 pcifunc, struct nix_txsch *txsch)
+{
+       struct rvu_hwinfo *hw = rvu->hw;
+       int lbk_link_start, lbk_links;
+       u8 pf = rvu_get_pf(pcifunc);
+       int schq;
+
+       if (!is_pf_cgxmapped(rvu, pf))
+               return;
+
+       lbk_link_start = hw->cgx_links;
+
+       for (schq = 0; schq < txsch->schq.max; schq++) {
+               if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
+                       continue;
+               /* Enable all LBK links with channel 63 by default so that
+                * packets can be sent to LBK with a NPC TX MCAM rule
+                */
+               lbk_links = hw->lbk_links;
+               while (lbk_links--)
+                       rvu_write64(rvu, blkaddr,
+                                   NIX_AF_TL3_TL2X_LINKX_CFG(schq,
+                                                             lbk_link_start +
+                                                             lbk_links),
+                                   BIT_ULL(12) | RVU_SWITCH_LBK_CHAN);
+       }
+}
+
 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
                                    struct nix_txschq_config *req,
                                    struct msg_rsp *rsp)
@@ -2040,6 +2069,9 @@ int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
                rvu_write64(rvu, blkaddr, reg, regval);
        }
 
+       rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc,
+                          &nix_hw->txsch[NIX_TXSCH_LVL_TL2]);
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index 3612e0a2cab324a2cf7405a841d19c89f63ee609..16c557cbe6a09b21a07074dd89b1e9e73bd03cff 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -468,6 +468,8 @@ static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 {
        int bank = npc_get_bank(mcam, index);
        int kw = 0, actbank, actindex;
+       u8 tx_intf_mask = ~intf & 0x3;
+       u8 tx_intf = intf;
        u64 cam0, cam1;
 
        actbank = bank; /* Save bank id, to set action later on */
@@ -488,12 +490,21 @@ static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
         */
        for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
                /* Interface should be set in all banks */
+               if (is_npc_intf_tx(intf)) {
+                       /* Last bit must be set and rest don't care
+                        * for TX interfaces
+                        */
+                       tx_intf_mask = 0x1;
+                       tx_intf = intf & tx_intf_mask;
+                       tx_intf_mask = ~tx_intf & tx_intf_mask;
+               }
+
                rvu_write64(rvu, blkaddr,
                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
-                           intf);
+                           tx_intf);
                rvu_write64(rvu, blkaddr,
                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
-                           ~intf & 0x3);
+                           tx_intf_mask);
 
                /* Set the match key */
                npc_get_keyword(entry, kw, &cam0, &cam1);

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
index 68633145a8b80956fc95199aa1057f66a1779853..92d64bdff0ea27aa2ac9c8073ccc3d703d17af28 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
@@ -949,9 +949,16 @@ static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,
                                struct npc_install_flow_req *req, u16 target)
 {
        struct nix_tx_action action;
+       u64 mask = ~0ULL;
+
+       /* If AF is installing then do not care about
+        * PF_FUNC in Send Descriptor
+        */
+       if (is_pffunc_af(req->hdr.pcifunc))
+               mask = 0;
 
        npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target),
-                        0, ~0ULL, 0, NIX_INTF_TX);
+                        0, mask, 0, NIX_INTF_TX);
 
        *(u64 *)&action = 0x00;
        action.op = req->op;