drm/msm/dpu: Remove unused INTF0 interrupt mask from SM6115/QCM2290
authorMarijn Suijten <marijn.suijten@somainline.org>
Wed, 26 Apr 2023 22:37:15 +0000 (00:37 +0200)
committerAbhinav Kumar <quic_abhinavk@quicinc.com>
Wed, 26 Apr 2023 23:46:30 +0000 (16:46 -0700)
Neither of these SoCs has INTF0, they only have a DSI interface on index
1.  Stop enabling an interrupt that can't fire.

Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115")
Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/534204/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h

index 6f04d8f85c9250ef65aa7b2bc3e628d497a0c275..988d820f7ef2e5e7059e368cdfed0777dcd516f8 100644 (file)
@@ -122,7 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                    BIT(MDP_INTF0_INTR) | \
                     BIT(MDP_INTF1_INTR),
 };
 
index 303492d62a5caaa38e39921289f35b672909a9c8..c9003dcc1a59b6221110b58bb9d4a0f930d30c0e 100644 (file)
@@ -112,7 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                    BIT(MDP_INTF0_INTR) | \
                     BIT(MDP_INTF1_INTR),
 };