ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576

Add constants and callback functions for the dwmac on RK3576 soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
[rebase, extracted bindings]
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20240823141318.51201-4-detlev.casanova@collabora.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9cf0aa58d13bf4f66c798cfc7681503d628e1aaa..50073bdade46e4bb481c85896d487472f97bd917 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1116,6 +1116,161 @@ static const struct rk_gmac_ops rk3568_ops = {
        },
 };
 
+/* VCCIO0_1_3_IOC */
+#define RK3576_VCCIO0_1_3_IOC_CON2             0X6408
+#define RK3576_VCCIO0_1_3_IOC_CON3             0X640c
+#define RK3576_VCCIO0_1_3_IOC_CON4             0X6410
+#define RK3576_VCCIO0_1_3_IOC_CON5             0X6414
+
+#define RK3576_GMAC_RXCLK_DLY_ENABLE           GRF_BIT(15)
+#define RK3576_GMAC_RXCLK_DLY_DISABLE          GRF_CLR_BIT(15)
+#define RK3576_GMAC_TXCLK_DLY_ENABLE           GRF_BIT(7)
+#define RK3576_GMAC_TXCLK_DLY_DISABLE          GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RX_DL_CFG(val)         HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3576_GMAC_CLK_TX_DL_CFG(val)         HIWORD_UPDATE(val, 0x7F, 0)
+
+/* SDGMAC_GRF */
+#define RK3576_GRF_GMAC_CON0                   0X0020
+#define RK3576_GRF_GMAC_CON1                   0X0024
+
+#define RK3576_GMAC_RMII_MODE                  GRF_BIT(3)
+#define RK3576_GMAC_RGMII_MODE                 GRF_CLR_BIT(3)
+
+#define RK3576_GMAC_CLK_SELECT_IO              GRF_BIT(7)
+#define RK3576_GMAC_CLK_SELECT_CRU             GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RMII_DIV2              GRF_BIT(5)
+#define RK3576_GMAC_CLK_RMII_DIV20             GRF_CLR_BIT(5)
+
+#define RK3576_GMAC_CLK_RGMII_DIV1             \
+                       (GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV5             \
+                       (GRF_BIT(6) | GRF_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV50            \
+                       (GRF_BIT(6) | GRF_CLR_BIT(5))
+
+#define RK3576_GMAC_CLK_RMII_GATE              GRF_BIT(4)
+#define RK3576_GMAC_CLK_RMII_NOGATE            GRF_CLR_BIT(4)
+
+static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
+                               int tx_delay, int rx_delay)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+       unsigned int offset_con;
+
+       if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
+               dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n");
+               return;
+       }
+
+       offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+                                        RK3576_GRF_GMAC_CON0;
+
+       regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
+
+       offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
+                                        RK3576_VCCIO0_1_3_IOC_CON2;
+
+       /* m0 && m1 delay enabled */
+       regmap_write(bsp_priv->php_grf, offset_con,
+                    DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+       regmap_write(bsp_priv->php_grf, offset_con + 0x4,
+                    DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+
+       /* m0 && m1 delay value */
+       regmap_write(bsp_priv->php_grf, offset_con,
+                    RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+                    RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+       regmap_write(bsp_priv->php_grf, offset_con + 0x4,
+                    RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+                    RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+}
+
+static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+       unsigned int offset_con;
+
+       if (IS_ERR(bsp_priv->grf)) {
+               dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+               return;
+       }
+
+       offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+                                        RK3576_GRF_GMAC_CON0;
+
+       regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
+}
+
+static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+       unsigned int val = 0, offset_con;
+
+       switch (speed) {
+       case 10:
+               if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
+                       val = RK3576_GMAC_CLK_RMII_DIV20;
+               else
+                       val = RK3576_GMAC_CLK_RGMII_DIV50;
+               break;
+       case 100:
+               if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
+                       val = RK3576_GMAC_CLK_RMII_DIV2;
+               else
+                       val = RK3576_GMAC_CLK_RGMII_DIV5;
+               break;
+       case 1000:
+               if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
+                       val = RK3576_GMAC_CLK_RGMII_DIV1;
+               else
+                       goto err;
+               break;
+       default:
+               goto err;
+       }
+
+       offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+                                        RK3576_GRF_GMAC_CON0;
+
+       regmap_write(bsp_priv->grf, offset_con, val);
+
+       return;
+err:
+       dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
+}
+
+static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
+                                      bool enable)
+{
+       unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
+                                  RK3576_GMAC_CLK_SELECT_CRU;
+       unsigned int offset_con;
+
+       val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
+                       RK3576_GMAC_CLK_RMII_GATE;
+
+       offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+                                        RK3576_GRF_GMAC_CON0;
+
+       regmap_write(bsp_priv->grf, offset_con, val);
+}
+
+static const struct rk_gmac_ops rk3576_ops = {
+       .set_to_rgmii = rk3576_set_to_rgmii,
+       .set_to_rmii = rk3576_set_to_rmii,
+       .set_rgmii_speed = rk3576_set_gmac_speed,
+       .set_rmii_speed = rk3576_set_gmac_speed,
+       .set_clock_selection = rk3576_set_clock_selection,
+       .regs_valid = true,
+       .regs = {
+               0x2a220000, /* gmac0 */
+               0x2a230000, /* gmac1 */
+               0x0, /* sentinel */
+       },
+};
+
 /* sys_grf */
 #define RK3588_GRF_GMAC_CON7                   0X031c
 #define RK3588_GRF_GMAC_CON8                   0X0320
@@ -1908,6 +2063,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
        { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
        { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
        { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
+       { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
        { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
        { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
        { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },