igc: Move the MULTI GBT AN Control Register to _regs file
authorSasha Neftin <sasha.neftin@intel.com>
Sun, 18 Aug 2024 08:32:50 +0000 (11:32 +0300)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Fri, 30 Aug 2024 14:44:39 +0000 (07:44 -0700)
MULTI GBT AN Control Register is IEEE Standard Register 7.32 (not a mask).
The right place should be in igc_reg.h file. In accordance with the
registers naming convention added IGC_' prefix.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Tested-by: Avigail Dahan <avigailx.dahan@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/igc/igc_defines.h
drivers/net/ethernet/intel/igc/igc_phy.c
drivers/net/ethernet/intel/igc/igc_regs.h

index 6d6717ba4ffdc9e24ed2a7e469376d4ec6dc614f..8e449904aa7dbd12ea1181c9635a909e4c50afda 100644 (file)
 
 /* PHY GPY 211 registers */
 #define STANDARD_AN_REG_MASK   0x0007 /* MMD */
-#define ANEG_MULTIGBT_AN_CTRL  0x0020 /* MULTI GBT AN Control Register */
 #define MMD_DEVADDR_SHIFT      16     /* Shift MMD to higher bits */
 #define CR_2500T_FD_CAPS       0x0080 /* Advertise 2500T FD capability */
 
index 861f37076861655df235fed77f6e7d0cb4bb3dc4..2801e5f24df902028f7321e9d1ccdb17b31310c2 100644 (file)
@@ -240,7 +240,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
                /* Read the MULTI GBT AN Control Register - reg 7.32 */
                ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
                                            MMD_DEVADDR_SHIFT) |
-                                           ANEG_MULTIGBT_AN_CTRL,
+                                           IGC_ANEG_MULTIGBT_AN_CTRL,
                                            &aneg_multigbt_an_ctrl);
 
                if (ret_val)
@@ -380,7 +380,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
                ret_val = phy->ops.write_reg(hw,
                                             (STANDARD_AN_REG_MASK <<
                                             MMD_DEVADDR_SHIFT) |
-                                            ANEG_MULTIGBT_AN_CTRL,
+                                            IGC_ANEG_MULTIGBT_AN_CTRL,
                                             aneg_multigbt_an_ctrl);
 
        return ret_val;
index bb6f37f5d3a534f4f802d17fcada4cf46ede3041..12ddc5793651d8694a68fff75da328bb91917fd7 100644 (file)
 #define IGC_IPCNFG     0x0E38 /* Internal PHY Configuration */
 #define IGC_EEE_SU     0x0E34 /* EEE Setup */
 
+/* MULTI GBT AN Control Register - reg. 7.32 */
+#define IGC_ANEG_MULTIGBT_AN_CTRL      0x0020
+
 /* EEE ANeg Advertisement Register - reg 7.60 and reg 7.62 */
 #define IGC_ANEG_EEE_AB1       0x003c
 #define IGC_ANEG_EEE_AB2       0x003e