KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access
authorRob Herring (Arm) <robh@kernel.org>
Wed, 31 Jul 2024 16:51:21 +0000 (10:51 -0600)
committerWill Deacon <will@kernel.org>
Fri, 16 Aug 2024 12:09:12 +0000 (13:09 +0100)
ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register
field. Make that clear by adding a standard sysreg definition for the
register, and using it instead.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: James Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-4-280a8d7ff465@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
arch/arm64/include/asm/sysreg.h
arch/arm64/kvm/sys_regs.c
arch/arm64/tools/sysreg
include/linux/perf/arm_pmuv3.h

index 4a9ea103817e896f9c0f74d2f4285fb0915c8835..00af1c331c1e670f344399362f1a039a874c60f8 100644 (file)
 #define SYS_PMCNTENCLR_EL0             sys_reg(3, 3, 9, 12, 2)
 #define SYS_PMOVSCLR_EL0               sys_reg(3, 3, 9, 12, 3)
 #define SYS_PMSWINC_EL0                        sys_reg(3, 3, 9, 12, 4)
-#define SYS_PMSELR_EL0                 sys_reg(3, 3, 9, 12, 5)
 #define SYS_PMCEID0_EL0                        sys_reg(3, 3, 9, 12, 6)
 #define SYS_PMCEID1_EL0                        sys_reg(3, 3, 9, 12, 7)
 #define SYS_PMCCNTR_EL0                        sys_reg(3, 3, 9, 13, 0)
index c90324060436b272fd0f7dde8e023a7911edcc7b..33497db257fb644cdf63de38429614de4dc34bbc 100644 (file)
@@ -887,7 +887,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
        reset_unknown(vcpu, r);
-       __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
+       __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
 
        return __vcpu_sys_reg(vcpu, r->reg);
 }
@@ -979,7 +979,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
        else
                /* return PMSELR.SEL field */
                p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
-                           & ARMV8_PMU_COUNTER_MASK;
+                           & PMSELR_EL0_SEL_MASK;
 
        return true;
 }
@@ -1047,8 +1047,8 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
                        if (pmu_access_event_counter_el0_disabled(vcpu))
                                return false;
 
-                       idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
-                             & ARMV8_PMU_COUNTER_MASK;
+                       idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
+                                           __vcpu_sys_reg(vcpu, PMSELR_EL0));
                } else if (r->Op2 == 0) {
                        /* PMCCNTR_EL0 */
                        if (pmu_access_cycle_counter_el0_disabled(vcpu))
@@ -1098,7 +1098,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 
        if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
                /* PMXEVTYPER_EL0 */
-               idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
+               idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
                reg = PMEVTYPER0_EL0 + idx;
        } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
                idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
index 7ceaa1e0b4bc25992165eac2f32e147fea465b31..37aa7eaad07bd8c40504ebc86f786007632c0d29 100644 (file)
@@ -2153,6 +2153,11 @@ Field    4       P
 Field  3:0     ALIGN
 EndSysreg
 
+Sysreg PMSELR_EL0      3       3       9       12      5
+Res0   63:5
+Field  4:0     SEL
+EndSysreg
+
 SysregFields   CONTEXTIDR_ELx
 Res0   63:32
 Field  31:0    PROCID
index eccbdd8eb98fcfd2a68104a473d2c10b4b226a08..792b8e10b72a01618a674d881593a49cfbafc3a7 100644 (file)
@@ -8,7 +8,6 @@
 
 #define ARMV8_PMU_MAX_GENERAL_COUNTERS 31
 #define ARMV8_PMU_MAX_COUNTERS 32
-#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
 
 /*
  * Common architectural and microarchitectural event numbers.