drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions

We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.

Bspec: 71265

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-5-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 2f1e3cb1a24772b6f91118d2630836c530592393..e16ea3f16ed88915f34961b2888088efc85830a0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -27,6 +27,14 @@
                                                   _MTL_PIPEDMC_EVT_CTL_4_A, \
                                                   _MTL_PIPEDMC_EVT_CTL_4_B)
 
+#define PIPEDMC_BLOCK_PKGC_SW_A        0x5f1d0
+#define PIPEDMC_BLOCK_PKGC_SW_B        0x5F5d0
+#define PIPEDMC_BLOCK_PKGC_SW(pipe)                            _MMIO_PIPE(pipe, \
+                                                                          PIPEDMC_BLOCK_PKGC_SW_A, \
+                                                                          PIPEDMC_BLOCK_PKGC_SW_B)
+#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS                        BIT(31)
+#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15)
+
 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A  0x5f000
 #define _TGL_PIPEDMC_REG_MMIO_BASE_A   0x92000