drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff

I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")

Bspec had the same exact thing to say about earlier hardware
as well, but we never cared and things work just fine.

The one thing mentioned in that commit that is definitely
true however is the fence alignment issue. But we don't
deal with that on earlier hardware either. We do have code
to deal with that issue for the first color plane, but not
the chroma planes. So I think if we did want to check this
more extensively we should do it in the same places where
we already check the first color plane (namely
convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()).

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-10-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index a11c1cf6f5489d1431a970acf50d45ae80a57050..f23547a88b1fb0648386cb1e8e053d2c9cb7f4a3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -585,12 +585,6 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl
        return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
 }
 
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
-{
-       return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
-               color_plane == 1;
-}
-
 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
        return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
@@ -1020,11 +1014,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
        struct drm_i915_private *i915 = to_i915(fb->dev);
        unsigned int height, alignment, unused;
 
-       if (DISPLAY_VER(i915) >= 12 &&
-           !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
-           is_semiplanar_uv_plane(fb, color_plane))
-               alignment = intel_tile_row_size(fb, color_plane);
-       else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+       if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
                alignment = intel_tile_size(i915);
        else
                alignment = 0;

diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 1b1fef2dc39a907b4fcda62b5169b6bf152679b6..6dee0c8b7f2264fd7bc3793e87fb59b4cb92fec8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,7 +34,6 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
 bool intel_fb_is_mc_ccs_modifier(u64 modifier);
 
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
 

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a1c4778cf6561009be9eccb2201978a76a0673f1..ba5a628b4757c110e3893d6e6233713d863d1281 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -515,20 +515,6 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane,
        if (intel_fb_is_ccs_aux_plane(fb, color_plane))
                return mult * 4 * 1024;
 
-       if (is_semiplanar_uv_plane(fb, color_plane)) {
-               if (intel_fb_uses_dpt(fb))
-                       return 512 * 4 * 1024;
-
-               /*
-                * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
-                * alignment for linear UV planes on all platforms.
-                */
-               if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
-                       return 256 * 1024;
-
-               return intel_tile_row_size(fb, color_plane);
-       }
-
        switch (fb->modifier) {
        case DRM_FORMAT_MOD_LINEAR:
        case I915_FORMAT_MOD_X_TILED: