drm/amdgpu - optimize rlc spm cntl

v1
- driver MMIO read the register to check whether write is required
- if write is required, sriov full time to use rlcg, otherwise use KIQ

v2
- include gfx v11 sriov runtime case

Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 953df202953a8b65a4fcd77761f72686d334b14d..1f516466ac13760c7590eba136cf425574b04f39 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8062,15 +8062,24 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
                                               unsigned int vmid)
 {
-       u32 data;
+       u32 reg, pre_data, data;
 
+       reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
        /* not for *_SOC15 */
-       data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
+       if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
+               pre_data = RREG32_NO_KIQ(reg);
+       else
+               pre_data = RREG32(reg);
 
-       data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
+       data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       if (pre_data != data) {
+               if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
+                       WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
+               } else
+                       WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       }
 }
 
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ad6431013c7386c2621821917c22892e54df2e38..e5882da8332aecea9fc395eeb18559735e3862b6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5030,24 +5030,31 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 
 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
 {
-       u32 data;
+       u32 reg, pre_data, data;
 
        amdgpu_gfx_off_ctrl(adev, false);
+       reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+       if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
+               pre_data = RREG32_NO_KIQ(reg);
+       else
+               pre_data = RREG32(reg);
 
-       data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
-
-       data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
+       data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
-
+       if (pre_data != data) {
+               if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
+                       WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
+               } else
+                       WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
+       }
        amdgpu_gfx_off_ctrl(adev, true);
 
        if (ring
                && amdgpu_sriov_is_pp_one_vf(adev)
+               && (pre_data != data)
                && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
                        || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
-               uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
                amdgpu_ring_emit_wreg(ring, reg, data);
        }
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 07b299ec7169fa26ba92f754c8ab122c93b6e26b..aecc2bcea1450fa05fb9f2ba6d57e309fbbfaf3c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1395,21 +1395,23 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                                       unsigned vmid)
 {
-       u32 reg, data;
+       u32 reg, pre_data, data;
 
        reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               data = RREG32_NO_KIQ(reg);
+       if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
+               pre_data = RREG32_NO_KIQ(reg);
        else
-               data = RREG32(reg);
+               pre_data = RREG32(reg);
 
-       data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
+       data =  pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
-       else
-               WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
+       if (pre_data != data) {
+               if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
+                       WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
+               } else
+                       WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
+       }
 }
 
 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {